John P. Fishburn

TILOS: A Posynomial Programming Approach to Transistor Sizing

A new transistor sizing algorithm, which couples synchronous timing analysis with convex optimization techniques, is presented. Let A be the sum of transistor sizes, T the longest delay through the circuit, and K a positive constant. Using a distributed RC model, each of the following three programs is shown to be convex: 1) Minimize A subject to T < K. 2) Minimize T subject to A < K. 3) Minimize AT K . The convex equations describing T are a particular class of functions called posynomials. Convex programs have many pleasant properties, and chief among these is the fact that any point found to be locally optimal is certain to be globally optimal TILOS (Timed Logic Synthesizer) is a program that sizes transistors in CMOS circuits. Preliminary results of TILOS’s transistor sizing algorithm are presented.

Clock skew optimization

Improving the performance of a synchronous digital system by adjusting the path delays of the clock signal from the central clock source to individual flip-flops is investigated. Using a model to detect clocking hazards, two linear programs are investigated: (1) minimizing the clock period, while avoiding clock hazards, and (2) for a given period, maximizing the minimum safety margin against clock hazard. These programs are solved for a simple example, and circuit simulation is used to contrast the operation of a resulting circuit with the conventionally clocked version. The method is extended to account for clock skew caused by relative variations in the drive capabilities of N-channel versus P-channel transistors in CMOS. >

Parallelism in alpha-beta search

We present a distributed algorithm for implementing α-β search on a tree of processors. Each processor is an independent computer with its own memory and is connected by communication lines to each of its nearest neighbors. Measurements of the algorithms performance on the Arachne distributed operating system are presented. A theoretical model is developed that predicts at least order of k12 speedup with k processors.

Shaping a distributed-RC line to minimize Elmore delay

Eulers differential equation of the calculus of variations is used to determine the shape of a distributed-RC wire that minimizes Elmore delay. In two dimensions the optimal shape is an exponential taper. In three dimensions the optimal shape is a frustum of a cone.

A depth-decreasing heuristic for combinational logic; or how to convert a ripple-carry adder into a carry-lookahead adder or anything in-between

This paper describes a heuristic for speeding up combinational logic by decreasing the logic depth, at the expense of a minimal increase in circuit size. The heuristic iteratively speeds up sections of the critical path by the use of Shannon factorization on the late input. This procedure is empirically found to be capable of reproducing or even beating several classic global optimizations: a chain of an associative operator is transformed into a tree, a ripple prefix circuit into a parallel prefix circuit, and a ripple-carry adder into a slightly smaller and faster circuit than the carry-lookahead adder.

LATTIS: an iterative speedup heuristic for mapped logic

The author describes heuristic problems for performance optimization of mapped combinational logic, implemented in the system LATTIS (logic area-time tradeoff for integrated systems). LATTIS currently has six transform types: gate repowering, buffer insertion, downpowering of noncritical fanouts of the critical path, gate duplication, DeMorgans laws, and timing-directed factorization and remapping of subcircuits. From among the transforms applicable on the critical path. LATTIS chooses the one with maximum benefit/cost. Cost is increase in area, and benefit is improvement in local slack, weighted by the number of primary input/outputs affected. The delay-area curves produced by LATTIS for the 70 largest circuits of the 1991 MCNC multilevel combinational logic benchmark set are given.<<ETX>>

Interconnect synthesis without wire tapering

Interconnect synthesis techniques, such as wire sizing and buffer insertion/sizing, have proven to be critical for reducing interconnect delays in deep submicron design. Consequently, the past few years have seen several works that study buffer insertion, wire sizing, and their simultaneous optimization. For long interconnect, wire tapering, i.e., reducing the wire width as the distance from the driver increases, can yield better solutions than uniform wire sizing. However, despite its obvious benefits, tapering is not widely used in practice since it is difficult to integrate into a coherent routing methodology. This paper studies the benefits of wire sizing with tapering when combined with buffer insertion. We first present a theoretical result that shows wire tapering is at most 3.5% faster than uniform wire sizing when maximal buffer insertion is applied. We then present detailed experiments that support this result. Consequently, we conclude that it is generally not worthwhile to perform tapering for signal nets. Finally, we present a general formulation and optimal polynomial time algorithm for simultaneous wire sizing and buffer insertion that forbids wire tapering, but incorporates layer assignment and wire spacing.

Shaping a VLSI wire to minimize Elmore delay

Eulers differential equation of the calculus of variations is used to determine the shape of a VLSI wire that minimizes Elmore delay. The solution is given as a power series whose coefficients are formulas involving the load-end wire width, the load capacitance, the capacitance per unit area, and the capacitance per unit perimeter. In contrast to an optimal-width rectangular wire, the RC Elmore delay of the optimally tapered wire goes to zero as the driver resistance goes to zero. The optimal taper is immune, to first order, to process variations affecting wire width.

Experiments using automatic physical design techniques for optimizing circuit performance

A system that accepts a transistor level net list, tunes it for high performance, and automatically lays it out is described. The system consists primarily of two components, TILOS and SC2D. The first component, TILOS, adjusts transistor sizes and reorders series devices to meet user-supplied performance specifications, while using the smallest size transistors possible. The sized net list is placed and routed by SC2D, which produces a virtual-grid layout ready for compaction. The algorithms and procedures are described, and their effect is illustrated with several examples, ranging from a few dozens of transistors to tens of thousands.<<ETX>>

Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization

Abstract: An algorithm for unifying the techniques of gate sizing and clock skew optimization for acyclic pipelines is presented. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure utilizes the idea of cycle-borrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. Experimental results verify that cycle-borrowing using sizing+skew results in a better overall area-delay tradeoff than with sizing alone.