Steven F. Oakland

An on-chip self-repair calculation and fusing methodology

Laser fusing is a standard technique for improving yield with memory reconfiguration and repair, but implementing fusing in production can be challenging and costly. This article introduces an electrically programmable polysilicon fuse and shows how it can reduce fuse area and programming complexity.

On-chip repair and an ATE independent fusing methodology

This paper describes a novel on chip repair system designed for ATE independent application on many unique very dense ASIC devices in a high turnover environment. During test, the system controls on chip built-in self-test (BIST) engines, collects and compresses repair data, programs fuses and finally decompresses and reloads the repair data for post fuse testing. In end use applications this system decompresses and loads the repair data at power-up or at the request of the system.

Considerations for implementing IEEE 1149.1 on system-on-a-chip integrated circuits

This paper addresses four issues associated with using IEEE Standard 1149.1 on system-on-a-chip integrated circuits (SOC ICs). First, a new, simplified method for accessing debug registers in processor cores embedded within ICs is presented. Second, structural information required by hardware/software processor development tools is presented. Third, issues associated with boundary-scan description language (BSDL) are discussed. Finally, high-speed boundary-scan cells that avoid a multiplexer delay are presented.

Combining IEEE Standard 1149.1 with reduced-pin-count component test

This paper describes a boundary-scan structure that permits comprehensive testing of level-sensitive-scan design (LSSD) components with high signal input/output (I/O) pin counts, using relatively inexpensive reduced-pin-count automatic testing equipment (ATE). Furthermore, the structure conforms to IEEE Standard 1149.1, Test Access Port and Boundary-Scan Architecture, which simplifies testing of assembled printed-circuit boards or other multi-component substrates.<<ETX>>

Why would an ASIC foundry accept anything less than full scan

A key force behind IBMs growth in the application-specific integrated circuit (ASIC) market is the ability to sign off on multi-million-gate designs without requiring test vectors, presenting a savings in both time and money to customers. Once a customer ensures (via formal verification and/or functional simulation) that the design functions as required, static tinting analysis (STA) ensures that the design achieves the required performance targets. Extensive model-to-hardware correlation assures correctness of the timing analysis models, enabling IBM to assure that the design can be manufactured to the required performance targets. Through a combination of full-scan and boundary-scan design-for-test (DFT) structures, the IBM ASIC methodology ensures that automatically generated test patterns will run correctly on test equipment; typically achieving 99+% stuck-fault coverage. In the case of a repeatable manufacturing defect, full-scan-based diagnostic software isolates the problem without customer involvement.

An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs

In contract manufacturing, the circuit netlist is owned by the ASIC customer. The manufacturer is required to work strictly within the design structure established by the customer. To manufacture high-quality components in this environment, it is critical to meet the customers mandated quality and performance criteria, while minimizing hardware overhead and introducing little or no design change. In this paper, the authors present a test framework for contract-manufactured ASICs using low-cost testers. Key aspects of the framework are low hardware overhead, significant savings in test data volume and test cost, and tight integration of the at-speed and ATE-driven test components to the design and manufacturing process.

OCI: Open Compression Interface

Before on-chip scan compression, it was possible to use different EDA tool vendors to do scan insertion, pattern generation, and diagnosis. On-chip scan compression changed that use model since each tool vendor supplied a different type of scan compression logic and had tool-specific ways to pass necessary information from scan insertion to pattern generation and from pattern generation to diagnosis. OCI (open compression interface) is a standardization of how the necessary data is passed from test logic insertion to pattern generation to diagnosis such that different vendors can be used for each step independent of the on-chip scan compression logic used. This document discusses the need for OCI and gives a conceptual overview of the OCI standard