Pamela S. Gillis

Low-cost testing of high-density logic components

The evolution of a testing method and architecture of a logic-device tester to be used for the next generation of IBMs high-density CMOS ASIC (application-specific integrated circuit) logic components is described. The testers design is based on the architecture of an existing IBM memory tester rather than on a conventional logic-tester design. The testing strategy calls for boundary-scan in each component design, built-in self-test logic within embedded memory arrays, and the use of weighted random-pattern logic testing. The development of the tester hardware is discussed, and capital costs of the new tester are compared with those of other approaches. >

Delay test of chip I/Os using LSSD boundary scan

This paper describes a novel design-for-test (DFT) concept for I/O delay testing while contacting very few pads, using boundary scan and new test-generation software. In production testing of the IBM System/390 Generation 3/sup TM/ and several ASIC chips, these patterns uncovered unique manufacturing defects.

Low cost testing of high density logic components

The authors describe the evolution and architecture of a logic device tester for the next generation of high-density logic components to be produced by IBM at its Essex Junction, Vermont, facility. The tester architecture is based on the design of an existing internal memory tester, rather than on the design of a conventional logic tester. This design point was an evolutionary outcome of a comprehensive logic test strategy development process. That strategy called for inclusion of boundary scan and array built-in self test in each component design, and for adoption of weighted random pattern logic testing (WRPT). WRPT enables tester data volumes to be reduced by two orders of magnitude in comparison with stored pattern logic testing, while simultaneously maintaining high test quality. The resulting tester architecture and design are described in the context of those decisions.<<ETX>>The evolution of a testing method and architecture of a logic-device tester to be used for the next generation of IBMs high-density CMOS ASIC (application-specific integrated circuit) logic components is described. The testers design is based on the architecture of an existing IBM memory tester rather than on a conventional logic-tester design. The testing strategy calls for boundary-scan in each component design, built-in self-test logic within embedded memory arrays, and the use of weighted random-pattern logic testing. The development of the tester hardware is discussed, and capital costs of the new tester are compared with those of other approaches.<<ETX>>

HIGH-DENSITY CMOS MULTICHIP-MODULE TESTING AND DIAGNOSIS

Muhichip-module ( M C M ) packages have been developed for use with high-density, high-performance CMOS chip technologies. The combination of CMOS and multichip packaging poses, new test-related challenges arising from the resulting v e 9 large circuit and signal inputloutput counts, and from CMOS-related reliability requirements. This paper discusses current practice and indicates jidture directions for MCM assembly, testing, and diagnosis.

Low overhead delay testing of ASICs

Delay testing has become increasingly essential as chip geometries shrink. Low overhead or cost effective delay test methodology is successful when it results in a minimal number of effective tests and eases the demands on an already burdened IC design and test staff. This work describes one successful method in use by IBM ASICs that resulted in a slight total test pattern increase, generally ranging between 10 and 90%. Example ICs showed a pattern increase of as little as 14% from the stuck-at fault baseline with a transition fault coverage of 89%. In an ASIC business, a large number of ICs are processed, which does not allow for the personnel to understand how to test each individual IC design in detail. Instead, design automation software that is timing and testability aware ensures effective and efficient tests. The resultant tests detect random spot timing delay defects. These types of defects are time zero related failures and not reliability wearout mechanisms.

A 300 K-circuit ASIC logic family CAD system

A computer-aided design (CAD) system has been developed to design CMOS application-specific integrated circuit (ASIC) logic family chips denser than any previously available, with performance comparable to bipolar technology. Design flow and key new features are described, and test chip results are given. Logic synthesis and transformation systems translate the designs to a technology-independent internal representation; optimize them for area, performance, and testability; and translate them to an implementation in the technology circuit library. The synthesis systems add logic circuits needed for testing and generate information about the clock trees used later in physical clock-free construction.<<ETX>>

A comprehensive CAD system for high-performance 300 K-circuit ASIC logic chips

A computer-aided design (CAD) system has been developed to support design of CMOS application-specific integrated circuit (ASIC) logic chips containing more than 300 K equivalent two-input NANDs with 180-ps typical gate delays. The underlying technology is a 0.8- mu m, four-level-metal, single-poly CMOS process, with a 0.45- mu m nominal effective channel length and 180-ps typical gate delay. Both standard-cell and gate-array circuit libraries are provided, including fixed and growable memory macros. Key new system features are described in the areas of high-level design and synthesis, delay calculation and timing analysis, timing guidance to physical design, physical design, clock construction, and test generation. Early processing results are reported for several test chips, including a 9.7-mm 2-million-transistor chip and a 14.5-mm 300 K-equivalent-gate chip. >