Lloyd G. Clonts

A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications

An integrated CMOS subnanosecond time-to-digital converter (TDC) has been developed and evaluated for positron emission tomography (PET) front-end applications. The TDC architecture combines an accurate digital counter and an analog time interpolation circuit to make the time interval measurement. The dynamic range of the TDC is programmable and can be easily extended without any timing resolution degradation. The converter was designed to operate over a reference clock frequency range of 62.5 MHz up to 100 MHz and can have a bin size as small as 312.5 ps LSB with 100-ns conversion times. Measurements indicate the TDC achieves a DNL of under /spl plusmn/0.20 LSB and INL less than /spl plusmn/0.30 LSB with an rms timing resolution of 0.312 LSB (97.5 ps), very close to the theoretical limit of 0.289 LSB (90 ps). The design is believed to be the first fully integrated CMOS subnanosecond TDC used in PET medical imaging and the first realization of a CMOS TDC that achieves an rms timing resolution below 100 ps within a 100-ns conversion time.

A multi-channel ADC for use in the PHENIX detector

A custom CMOS analog to digital converter was designed and a prototype 8-channel ADC ASIC was fabricated in a 1.2 /spl mu/m process. The circuit uses a Wilkinson-type architecture which is suitable for use in multi-channel applications such as the PHENIX detector. The ADC design features include a differential positive-ECL input for the high speed clock and selectable control for 11 or 12-bit conversions making it suitable for use in multiple PHENIX subsystems. Circuit topologies and ASIC layout specifics, including power consumption, maximum clock speed, INL, and DNL are discussed. The ADC performed to 11-bit accuracy.

Monolithic circuits for the WA98 lead class calorimeter

Two monolithic circuits developed for readout of a 10000 element lead glass calorimeter are described. The first contains 8 channels with each channel comprising a charge integrating amplifier, two output amplifiers with gains of one and eight, a timing filter amplifier and a constant fraction discriminator. This IC also contains a maskable, triggerable calibration pulser and circuits needed to form 2 by 2 and 4 by 4 energy sums used to provide trigger signals. The second IC is a companion to the first and contains 16 analog memory channels with 16 cells each, eight time-to-amplitude converters and a 24-channel analog-to-digital converter. The use of the analog memories following the integration function eliminates the need for delay cables preceding it. Characterizations of prototypes are reported, and features included to ease integration of the ICs into a readout system are described.<<ETX>>

A micropower CMOS, direct-conversion, VLF receiver chip for magnetic-field wireless applications

A micropower CMOS, direct-conversion very low frequency (VLF) receiver is described for receiving low-level magnetic fields from resonant sensors. The single-chip, phase locked loop (PLL)-synthesized receiver covers a frequency range of 10-82 kHz and provides both analog and 9-b digital baseband I and Q outputs. Digital I and Q outputs are accumulated in a companion digital chip which provides baseband signal processing. Emphasis is plated on the receiver micropower RF preamplifier which uses a lateral bipolar input device because of the significant increase in flicker noise illustrated for PMOS devices in weak inversion. Lateral bipolar transistors are also utilized in the mixer and IF stages for low flicker noise and low dc offsets. Special attention is given to isolating the internal local oscillator signals from the low-level RF input (0.3 /spl mu/V noise floor in 300 Hz BW), and local oscillator feedthrough is indiscernible in the RF preamplifier output noise spectrum. The 100% duty-cycle receiver, intended for miniature, battery-operated wireless applications, operates approximately four months at 80 /spl mu/A from a 6-V, 220-mA-hr battery.

Wavelength-shifting-fiber scintillation detectors for thermal neutron imaging at SNS

We have developed a wavelength-Shifting-fiber Scintillator Detector (SSD) with a 0.3 m2 area per module. Each module has 154 × 7 pixels and a 5 mm × 50 mm pixel size. Our goal is to design a large area neutron detector offering higher detection efficiency and higher count-rate capability for Time-Of-Flight (TOF) neutron diffraction in the Spallation Neutron Source (SNS). A ZnS/6LiF scintillator combined with a novel fiber encoding scheme (v.3) was used to record the neutron events. A Cross-fiber Read-Out-Card (CROC) based digital-signal processing electronics and position-determination algorithm was applied for neutron imaging. Neutron-gamma discrimination was carried out using Pulse-Shape Discrimination (PSD). A sandwiched flat scintillator detector can have a detection efficiency close to He-3 tubes (about 10 atm). A single layer and sandwiched flat scintillator detectors have count rate capabilities of about 6,000 and 35,000 cps/cm2, respectively, which can satisfy the count rate requirement of powder diffractometers at SNS. Detectors with v.3 fiber encoding have better image quality and higher spatial resolution than those with previous v.2 fiber encoding.

ASIC for Small Angle Neutron Scattering Experiments at the SNS

We present an ASIC for a 3He gas detector to be used in small angle neutron scattering experiments at the Spallation Neutron Source in Oak Ridge. The ASIC is composed of 64 channels with low noise charge amplification, filtering, timing and amplitude measurement circuits, where an innovative current-mode peak-detector and digitizer (PDAD) is adopted. The proposed PDAD provides at the same time peak detection and A/D conversion in real time, at low power, and without requiring a clock signal. The channels share an efficient data sparsification and derandomization scheme, a 30-bit 256 deep FIFO, and low voltage differential signaling.

First Measurements of the Inclined Boron Layer Thermal-Neutron Detector for Reflectometry

A prototype detector based on the inclined boron layer principle is introduced. For typical measurement conditions at the Liquids Reflectometer at the Spallation Neutron Source, its count rate capability is shown to be superior to that of the current detector by nearly two orders of magnitude.

TGLD: a 16 channel charge readout chip for the PHENIX Pad Chamber detector subsystem at RHIC

This paper describes TGLD, a charge readout chip for the PHENIX Pad Chamber (PC) subsystem at Brookhaven National Laboratorys Relativistic Heavy Ion Collider (RHIC) in Upton, NY. Due to the PCs high channel density, the TGLD and associated circuitry operate within the active detector region as permanent, zero access components, with remote set-up and test during collider operation. The TGLD design accommodates varying pad capacitance and charge gain for three detector subassemblies that detect particles at three different distances from the PHENIX collision vertex. The design also provides adjustable discrimination thresholds from MIP/10 to 2 MIP (Minimum Ionizing Particle). Three TGLD chips operate with a complimentary digital memory unit (DMU) to form 48 channel low power, low mass, readout cards. Partitioning of readout electronics and address control for robust remote operation are discussed. Component and system test results are also reported.

Timing and control requirements for a 32-channel AMU-ADC ASIC for the PHENIX detector

A custom CMOS Application Specific Integrated Circuit (ASIC) has been developed consisting of an analog memory unit (AMU) and analog to digital converter (ADC), both of which have been designed for applications in the PHENIX experiment. This IC consists of 32 pipes of analog memory with 64 cells per pipe. Each pipe also has its own ADC channel. Timing and control signal requirements for optimum performance are discussed in this paper.

Thermal neutron detectors with discrete anode pad readout

A new two-dimensional thermal neutron detector concept that is capable of very high rates is being developed. It is based on neutron conversion in 3He in an ionization chamber (unity gas gain) that uses only a cathode and anode plane; there is no additional electrode such as a Frisch grid. The cathode is simply the entrance window, and the anode plane is composed of discrete pads, each with their own readout electronics implemented via application specific integrated circuits. The aim is to provide a new generation of detectors with key characteristics that are superior to existing techniques, such as higher count rate capability, better stability, lower sensitivity to background radiation, and more flexible geometries. Such capabilities will improve the performance of neutron scattering instruments at major neutron user facilities. In this paper, we report on progress with the development of a prototype device that has 48 × 48 anode pads and a sensitive area of 24cm × 24cm.