Mary P. Kusko

Advanced microprocessor test strategy and methodology

This paper describes the overall test methodology used in implementing the S/390® microprocessor and the associated L2 cache array in shared multiprocessor designs, the design-for-test implementations, and the test software used in creating the test patterns and in measuring test effectiveness. Microprocessor advances in architectural complexity, circuit density, cycle time, and technology-related issues, coupled with IBMs high requirements for quality, reliability, and diagnosability, have made it necessary to develop testing methods and attain quality levels that far exceed what others have approached.

Diagnostic techniques for the IBM S/390 600 MHz G5 microprocessor

This paper describes strategies and techniques used to diagnose failures in the IBM 600 MHz G5 (Generation 5) CMOS microprocessor and associated cache chips. Time-to-market pressure demands quick diagnostic turnaround time while the complexity, density, cycle time, and technology issues of the hardware increase the difficulty of diagnosis. Since G5 first silicon, intense diagnostics and physical failure analysis (PFA) have successfully identified the root cause of many failures, including examples of process, design, and random manufacturing defects. This success is attributed to the three techniques described in this paper. For each technique, an example is presented to demonstrate its effectiveness.

Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip

This paper describes the test tool methodology used for the IBM S/390 microprocessor. An efficient, effective, and automated process providing correct-by-construction test pattern generation, an effective test pattern set, and diagnostics were required. This paper explains the techniques used to accomplish this along with explaining why the method was chosen and how it helped expedite the process.

Testing the 400 MHz IBM generation-4 CMOS chip

This paper describes the design-for-test framework of the 400 MHz CMOS central processor (CP) used in the fourth generation (G4) of the IBM S/390(R) line of servers. It will describe details of modeling logic to achieve correct and effective tests as well as describe the test sets required to test all portions of the design. This includes built-in self-test, array self-test, weighted random pattern generation, algorithmic pattern generation, and manual patterns. Tests are used to detect faults, static and dynamic, and to debug/diagnose chip failures characteristic to the function under test. The described tests ensure the highest reliability for the components within the system and the same test patterns can be applied from manufacturing all the way to the system level.

Low cost test point insertion without using extra registers for high performance design

This paper presents a new approach to improve random test coverage during physical synthesis for high performance design. This new approach performs test point insertion (TPI) to improve testability of random resistant nets. Conventional test point insertion approaches add extra registers either as control points or observation points to improve controllability or observability. However, adding extra registers has many disadvantages in high performance design. It might degrade the design performance in term of power and timing. It might also end up with even worse testability. The new approach does not add any registers; instead it only uses existing signals as test points. The test points are selected from logic paths with the most timing slack and physical placement proximity. This saves silicon area, reduces power consumption, and minimizes the design changes. The new approach also automates the test insertion process by integrating it in the physical synthesis flow. The integration helps reduce design closure turn around time significantly. Production results show nearly zero performance degradation from this approach and better testability improvement as compared to a manual test point insertion approach. Furthermore, this paper proposes a novel idea of exploiting unreachable states for test point insertion. Preliminary results on this idea are also given.

S/390 G5 CMOS microprocessor diagnostics

This paper describes the strategies and techniques used to diagnose failures in the IBM 600-MHz S/390® G5 (Generation 5) CMOS microprocessor and the associated cache chips. The complexity, density, cycle time, and technology issues related to the hardware, coupled with time-to-market requirements, have necessitated a quick diagnostic turnaround time. Beginning with the first prototype of the G5 microprocessor chip, intense chip diagnostics and physical failure analysis (PFA) have successfully identified the root causes of many failures, including process, design, and random manufacturing defects. In this paper, three different diagnostic techniques are described that have enabled the G5 to achieve its objective. An example is presented for each technique to demonstrate its effectiveness.

Testing the 500-MHz IBM S/390 microprocessor

The design-for-test framework of the 500-MHz CMOS central processor uses specific tests to ensure the highest reliability of components within a system. Some of the same test patterns are applied in chip manufacturing and system-level tests.

Cost trade-offs of various design for test techniques

Test cost is becoming a major factor in todays complex chip designs. One approach to lower test cost is to have the product test, or help test, itself. There are a wide variety of Design-for-Test techniques that have been developed for this purpose. A number of these techniques are evaluated against various related cost issues.

Structural and functional test of IBM system z10 chips

For the first time in the history of the IBM System z™ family of mainframes, System z10™ processor chips are tested by both structural and functional means. This complementary strategy starts at wafer test and is consistent through system test. In this paper, we describe how traditional and enhanced structured patterns provide fault coverage and how functional patterns mimic real system workloads. A new operating kernel generates functional tests and expected results and it can run these tests for either a finite or an indefinite amount of time to simulate system operation. It also executes custom hand-loop patterns to stress chip temperature and power. Both structural and functional patterns are used to uniquely characterize each chip. Adaptive algorithms based on results at wafer test determine optimal system operating voltage for each chip--a strategy that delivers a chip supply with optimal characteristics for system manufacturing and product delivery. The diversity of structural and functional patterns makes it possible to increase z10™ chip quality and reduce development time. The ability to run the same tests from wafer through system test provides a consistency not previously possible.

Testing the IBM Power 7™ 4 GHz eight core microprocessor

The IBM Power 7™ 4 GHz, eight core microprocessor introduced several new challenges for the Power 7 test team: new pervasive test architecture, 8 asynchronous processor cores, DRAM integrated on the same die as processor and enhanced thermal test requirements. The design complexity, time to market schedule compression, and rapid production ramp required innovation and new methods to meet these challenges. The following is an overview of the design for test architecture, manufacturing test methodology, thermal calibration, and rapid yield learning deployed to address these challenges and deliver a leadership server processor.