Bryan J. Robbins

Advanced microprocessor test strategy and methodology

This paper describes the overall test methodology used in implementing the S/390® microprocessor and the associated L2 cache array in shared multiprocessor designs, the design-for-test implementations, and the test software used in creating the test patterns and in measuring test effectiveness. Microprocessor advances in architectural complexity, circuit density, cycle time, and technology-related issues, coupled with IBMs high requirements for quality, reliability, and diagnosability, have made it necessary to develop testing methods and attain quality levels that far exceed what others have approached.

Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip

This paper describes the test tool methodology used for the IBM S/390 microprocessor. An efficient, effective, and automated process providing correct-by-construction test pattern generation, an effective test pattern set, and diagnostics were required. This paper explains the techniques used to accomplish this along with explaining why the method was chosen and how it helped expedite the process.

Testing the 400 MHz IBM generation-4 CMOS chip

This paper describes the design-for-test framework of the 400 MHz CMOS central processor (CP) used in the fourth generation (G4) of the IBM S/390(R) line of servers. It will describe details of modeling logic to achieve correct and effective tests as well as describe the test sets required to test all portions of the design. This includes built-in self-test, array self-test, weighted random pattern generation, algorithmic pattern generation, and manual patterns. Tests are used to detect faults, static and dynamic, and to debug/diagnose chip failures characteristic to the function under test. The described tests ensure the highest reliability for the components within the system and the same test patterns can be applied from manufacturing all the way to the system level.

Testing the 500-MHz IBM S/390 microprocessor

The design-for-test framework of the 500-MHz CMOS central processor uses specific tests to ensure the highest reliability of components within a system. Some of the same test patterns are applied in chip manufacturing and system-level tests.

Structural and functional test of IBM system z10 chips

For the first time in the history of the IBM System z™ family of mainframes, System z10™ processor chips are tested by both structural and functional means. This complementary strategy starts at wafer test and is consistent through system test. In this paper, we describe how traditional and enhanced structured patterns provide fault coverage and how functional patterns mimic real system workloads. A new operating kernel generates functional tests and expected results and it can run these tests for either a finite or an indefinite amount of time to simulate system operation. It also executes custom hand-loop patterns to stress chip temperature and power. Both structural and functional patterns are used to uniquely characterize each chip. Adaptive algorithms based on results at wafer test determine optimal system operating voltage for each chip--a strategy that delivers a chip supply with optimal characteristics for system manufacturing and product delivery. The diversity of structural and functional patterns makes it possible to increase z10™ chip quality and reduce development time. The ability to run the same tests from wafer through system test provides a consistency not previously possible.

A 32nm 0.5V-supply dual-read 6T SRAM

Dual read port SRAMs play a critical role in high performance cache designs, but stability and sensing challenges typically limit the low voltage operation. We report a high-performance dual read port 8-way set associative 6T SRAM with a one clock cycle access latency, in a 32nm metal-gate partially depleted (PD) SOI technology, for low-voltage applications. Hardware exhibits robust operation at 348MHz and 0.5V with a read and write power of 3.33 and 1.97mW, respectively, per 4.5KB active array with both read ports accessed at the highest activity data pattern. At a 0.6V supply, an access speed of 1.2GHz is observed.