Dong-Kyu Lee

Impact of floating gate dry etching on erase characteristics in NOR flash memory

We report the effects of plasma process-induced damage during floating gate (FG) dry-etching process on the erase characteristics of NOR flash cells. As compared to flash cells processed in a stable plasma condition, it is found that flash cells processed in the nonoptimized ambient show significantly degraded erase characteristics under a negative gate Fowler-Nordheim (FN) bias, exhibiting a fast-erasing bit in the distribution of erased bits. However, little differences are found in their tunneling characteristics under a positive gate biasing. The gate bias polarity dependence of FN tunneling indicates that positive charges are created near the poly-Si/SiO/sub 2/ interface during the FG dry-etching, prior to the backend processes such as metal- or via-etch.

A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies

This paper reports the design and fabrication of a practical Si nanowire (NW) transistor for beyond 10 nm logic devices application. The dependency of the DC and AC performances of Si NW MOSFETs on NW diameter (DNW) and gate oxide thickness has been investigated. A Si NW device with the scaled DNW of 9 nm and thin equivalent oxide thickness (EOT) of 0.9 nm improved both on-current and electrostatic characteristics. Finally, a Nanowire-On-Insulator (NOI) structure has been proposed to enhance the AC performance of a multiple-stacked NWs structure, which improves DC performance but has the issue of high parasitic capacitance. As a result, the simulated AC performance of a triple-NOI structure was improved by around 20% compared to conventional triple NW structure.

Mobile ion-induced data retention failure in NOR flash memory cell

Data retention failures due to nonoptimized processes in NOR-type flash memory cells are presented. Contrary to the charge leakage through defective oxide dielectric surrounding the floating gate, the data loss observed depends on whether the bit line contact is close to the cell or not. It is found that the data loss exhibits a charge-state dependence during baking stresses as well as temperature dependence. Based on experimental results, sodium movement in sidewall spacers is established as an origin for the data retention failure in NOR-type flash memory cells. Employing a thin nitride overlayer results in a good data retention, supporting the hypothesis of sodium movement.

48.3: A 2 Inch LTPS AMOLED with an Embedded Lateral p-i-n Photodiode Sensors

We developed a 2 inch low temperature poly-Si active-matrix organic light-emitting diode (AMOLED) with an embedded p-i-n photodiode. The pixels for both OLED and photodiode are designed using poly-Si TFT and poly-Si p-i-n. The lateral p-i-n photodiode exhibited the photo response of ∼40 dB under 100 lux. We have demonstrated the display and sensors successfully on glass. This technology can be used for AMOLED integrated with touch sensor and brightness control sensor.

Influence of plasma edge damage on erase characteristics of NOR flash EEPROM using channel erase method

We report the impact of plasma edge damage on erase characteristics in NOR Flash cells where channel erase is employed. Anomalous over-erased bits were observed, and they appeared to be associated with the creation of positive traps near the floating gate edge in the tunneling oxide layer during the plasma etch process. By examining possible processes and analyzing the erase characteristics, we have concluded that plasma edge damage is the cause of the anomalous erase behavior. Since the size of the damaged region does not decrease as the stacked gate channel length is scaled down, we foresee this defect as a serious limitation to future devices, especially Flash EEPROM.

Data retention failure in NOR flash memory cells

We present the results of investigations into the causes of threshold voltage instabilities in NOR-type flash memory cells due to charge loss and charge gain. A large threshold voltage shift of several volts has been observed on specific cells, which have a bit line contact that is misaligned and touches the side wall spacer. This data retention failure is characterized by both a temperature dependence of charge loss, showing an activation energy of about 1.12 eV, and a dependence of the magnitude of charge gain on the charged state in previous retention bake stressing. Employing a thin silicon nitride layer between the side wall spacer and the bit line contact results in good data retention. Based on these results, sodium ion contamination is proposed as the origin of charge loss and charge gain in NOR-type flash cells fabricated using a non-optimized process.