Keon-Soo Kim

Direct Field Effect of Neighboring Cell Transistor on Cell-to-Cell Interference of nand Flash Cell Arrays

We introduce the concept of the direct field effect of a neighboring cell transistor on the cell-to-cell interference of NAND Flash cell memory. As the cell size reduces to below 50 nm, the electric field of the adjacent cell transistor directly influences the shallow-trench isolation corner of a selected cell transistor, provoking a significant cell V TH shift. In a way different from how conventional parasitic capacitance-coupling effect alters only the floating gate voltage, the direct field effect changes the cell V TH intrinsically and provokes an intense V TH shift, particularly in word-line direction (x-direction), due to severe boron segregation on a channel edge. In a 45-nm design-rule nand Flash cell, this effect provokes 0.67 V of the V TH shift in the x-direction, while a conventional capacitance-coupling effect yields 0.28 V.

Impact of floating gate dry etching on erase characteristics in NOR flash memory

We report the effects of plasma process-induced damage during floating gate (FG) dry-etching process on the erase characteristics of NOR flash cells. As compared to flash cells processed in a stable plasma condition, it is found that flash cells processed in the nonoptimized ambient show significantly degraded erase characteristics under a negative gate Fowler-Nordheim (FN) bias, exhibiting a fast-erasing bit in the distribution of erased bits. However, little differences are found in their tunneling characteristics under a positive gate biasing. The gate bias polarity dependence of FN tunneling indicates that positive charges are created near the poly-Si/SiO/sub 2/ interface during the FG dry-etching, prior to the backend processes such as metal- or via-etch.

Integration Technology of 30nm Generation Multi-Level NAND Flash for 64Gb NAND Flash Memory

Multi-level NAND flash memories with a 38 nm design rule have been successfully developed for the first time. A breakthrough patterning technology of Self Aligned Double Patterning (SADP) together with ArF lithography is applied to three critical lithographic steps. Other key integration technologies include low thermal budget ILD process and twisted bit-line contact for excellent isolation between adjacent bit lines. Hemi-Cylindrical FET (HCFET) together with charge trapping memory cell of Si/SiO2 /SiN/Al2O3/TaN (TANOS) was found to be effective in sufficing various electrical requirements of 30 nm generation flash cells. Finally, MLC operation is successfully demonstrated with flash cells of 8 Gb density in which all the technologies aforementioned are combined.

A process technology for 1 giga-bit DRAM

In this paper, we present a giga bit density DRAM technology based on the state-of-the-art technologies. A DRAM with 1 giga bit density design rule is fabricated featuring Shallow Trench Isolation (STI), TiSi/sub x/ gate, Self-Aligned Contact (SAG), and simple stack capacitor cell using (Ba,Sr)TiO/sub 3/ (BST) as a dielectric material. A reliable and highly manufacturable process is established which satisfies the stringent requirement for the next generation memory devices such as 1 Gbit DRAM and beyond.

The Effect of Trapped Charge Distributions on Data Retention Characteristics of nand Flash Memory Cells

We present this letter on the combining effect of tunnel-oxide degradation and narrow width effect on the data retention characteristics of NAND flash memory cells. Due to severe boron segregation in shallow-trench isolation (STI) corner, the cell transistor suffers from intense VTH shift on STI corner in data retention mode. Independent of enhancing the tunnel-oxide quality, the data retention characteristics are improved by designing a cell transistor that isolates the region where Fowler-Nordheim stress mainly occurs in tunnel oxide away from STI corner. Experimental results show that VTH shift is reduced by 0.3 V or more in retention mode as the tunneling is separated from the isolation edge.

A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology

Recently, the demand for 3b/cell NAND flash has been increasing due to a strong market shift from 2b/cell to 3b/cell in NAND flash applications, such as USB disk drives, memory cards, MP3 players and digital still cameras that require cost-effective flash memory. To further expand the 3b/cell market, high write and read performances are essential [1]. Moreover, the device reliability requirements for these applications is a challenge due to continuing NAND scaling to sub-30nm pitches that increases cell-to-cell interference and disturbance. We present a high reliability 64Gb 3b/cell NAND flash with 7MB/s write rate and 200Mb/s asynchronous DDR interface in a 20m-node technology that helps to meet the expanding market demand and application requirement.

The Effect of Negative

We present our study on the dependence of data retention characteristics on the threshold voltage (V TH) of the cell transistor revealing the combined effect of control gate voltage and cell transistor architecture. Data retention characteristics are improved by designing a cell transistor that isolates the region where Fowler-Nordheim (FN) stress mainly occurs in tunnel oxide away from the region where maximum cell on-current flows. In the sub-50-nm region, due to short distance between the control gate and the shallow-trench isolation (STI) corner, the maximum cell on-current position is shifted from the STI corner to the channel center as control gate voltage decreases. The edge-thin tunnel oxide cell transistor, of which cell on-current flow is separated from tunneling current in negative cell V TH, shows 0.12-V superior data retention characteristic than the edge-thick tunnel oxide cell transistor at -3 V of cell transistor V TH in experiment.

V_{\rm TH}

In this paper, a 0.13 /spl mu/m DRAM technology is developed with KrF lithography. In order to extend KrF lithography to 0.13 /spl mu/m generation, full CMP technology is developed in order to provide flat surface. Full self-aligned contact (SAC) technology can make memory cell processes easy because memory cell landing pads and storage node contact plug can be formed with self-aligned manner respect to word-line and bit-line. By these technologies, the extremely small memory cell is easily realized without any yield loss. Low-temperature PAOCS MIS capacitor with Al/sub 2/O/sub 3/ can greatly reduce the aspect ratio of metal contact, thereby yielding stable metal contact process. And it can help DRAM technology easily to merge with logic process. The 0.13 /spl mu/m integration technology is successfully demonstrated with 1 Gb DRAM.

of nand Flash Memory Cells on Data Retention Characteristics

We present our study on the effect of field oxide recess on cell-programming-speed uniformity of nand flash cell memory. Due to the short distance between the control gate and the shallow-trench-isolation (STI) edge, the control-gate voltage generates uniform distribution of an electric field on the STI edge and provides strong immunity to fabrication process variation in cell programming. Therefore, the optimized field oxide recess offers an inherently narrower cell V TH distribution, fastening multilevel-cell programming speed while minimizing the floating-gate interference. Experimental results on 63-nm cell arrays show that the cell V TH distribution is reduced by 18% or more as field oxide recess increases.

A 0.13 /spl mu/m DRAM technology for giga bit density stand-alone and embedded DRAMs

A highly manufacturable multi-level NAND flash memory with a 27nm design rule has been successfully developed for the first time. Its unit cell size is 0.00375um2 (with overhead). Self Aligned Reverse Patterning is used to improve initial Vth distribution induced from DPT (Double Patterning Technology) process. By using advanced channel doping technique, the channel junction leakage is minimized and the Vpass window is improved. The optimized doping structure and cell operation scheme are evaluated. And finally 2 and 3bit per cell operation are successfully demonstrated with flash cells of 32Gb density with reasonable reliability.