Dong-Soo Jun

Temperature-compensation circuit techniques for high-density CMOS DRAMs

Temperature-compensation circuit techniques are presented for the CMOS DRAM internal voltage converter, the RC-delay circuit, and the back-bias generator, which do not need any additional process steps. The above-mentioned circuits have been designed and evaluated through a 16-Mb CMOS DRAM process. These circuits have shown an internal voltage converter (IVC) with an internal voltage temperature coefficient of 185 ppm/ degrees C, and an RC-delay circuit with a delay time temperature coefficient of 0.03%/ degrees C. As a result, a 6.5-ns faster RAS access time and improved latchup immunity have been achieved, compared with conventional circuit techniques. >

Battery Operated 16m Dram With Post Package Programmable And Variable Self Refresh

with wide operating voltage range of 1.8~ to 3.6~ for battery based portable applications. Low power during data retention is obtained with Vcc and temperature variable self refresh which is programmable after packaging using electrical fuses. High performance is achieved at low voltage with dual VPPs for well bias and on-chip high voltage power supply, dual threshold voltages for NMOS and voltage variable sensing control. The 16M has a measured RAS access time of 58ns at 1.8~ and 83°C. This paper describes a I6M DRAM

A 35 ns 64 Mb DRAM using on-chip boosted power supply

An on-chip boosted power supply is necessary for ease of layout and high speed in high density DRAMs. The technique of TTL conversion is a key to designing high speed DRAMs for 3-V operation. The authors present the generation and regulation of an on-chip power supply (V/sub pp/) within 50 mV of the optimum level during operation for a given V/sub cc/. In addition to the regulated V/sub cc/ scheme, improved interface circuit techniques are employed to achieve fast input and output conversion with good noise margins. An experimental 64-Mb DRAM is designed. A typical access time of 35 ns is obtained by measurement.<<ETX>>