Dae-Je Chin

Variable V/sub CC/ design techniques for battery-operated DRAMs

Wide-voltage-range DRAMs with extended data retention are desirable for battery-operated or portable computers and consumer devices. The techniques required to obtain wide operation, functionality, and performance of standard DRAMs from 1.8 V (two NiCd or alkaline batteries) to 3.6 V (upper end of LVTTL standard) are described. Specific techniques shown are: (1) a low-power and low-voltage reference generator for detecting V/sub CC/ level; (2) compensation of DC generators, V/sub BB/ and V/sub PP/, for obtaining high speed at reduced voltages; (3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and (4) a programmable V/sub CC/ variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16 M DRAM (2 M*8) by simulation. >

Temperature-compensation circuit techniques for high-density CMOS DRAMs

Temperature-compensation circuit techniques are presented for the CMOS DRAM internal voltage converter, the RC-delay circuit, and the back-bias generator, which do not need any additional process steps. The above-mentioned circuits have been designed and evaluated through a 16-Mb CMOS DRAM process. These circuits have shown an internal voltage converter (IVC) with an internal voltage temperature coefficient of 185 ppm/ degrees C, and an RC-delay circuit with a delay time temperature coefficient of 0.03%/ degrees C. As a result, a 6.5-ns faster RAS access time and improved latchup immunity have been achieved, compared with conventional circuit techniques. >

An experimental 16-Mbit DRAM with reduced peak-current noise

An experimental 16-Mbit CMOS DRAM with die size of 8.52 X18.4 mm2 has been developed. A trenched and saddled stack capacitor (TSSC) cell was invented, and storage capacitance of 30fF was obtained in a cell size of 1.65 x 3.339 ?spl mu/m2. Peak-current noise on the power buses during the sense-amplifier latching is suppressed by distributing large numbers of pull-down and pull-up drivers in memory core arrays. Two 4-V internal Vcc converters are used separately for peripheral and core array circuits. The reference voltage generator employs a bandgap reference circuit whose temperature stability is better than conventional MOS diode references.

16-Mb synchronous DRAM with 125-Mbyte/s data rate

In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 16M SDRAM (2M/spl times/8) achieves a 125-Mbyte/s data rate using 0.5-/spl mu/m twin well CMOS technology. >

16 Mbit synchronous DRAM with 125 Mbyte/sec data rate

The rapid increase in processor performance and memory density has created the need for high bandwidth DRAM for a variety of applications. A 3.3V 2M x8 synchronous DRAM is designed with a typical data rate of 125 Mbyte/sec using internal column address sequencing, pipelined 2 bit prefetch and variable output latching scheme. It supports operating frequencies up to 125 MHz.

Wordline coupling noise reduction techniques for scaled DRAMs

The wordline architecture of the twisted word line (TWL) scheme and a wordline latch circuit for suppressing wordline coupling noise have been proposed and demonstrated. Using this approach, wordline coupling noise is reduced by 70% compared to the conventional wordline structure. This technique was found to be effective for suppressing wordline coupling noise with minimum layout penalty in scaled high-density DRAMs