Douglas Chang

Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs

We investigate the hardware implications when combinational logic is implemented on Dynamically Reconfigurable FPGAs (DRFPGAs). We first investigate the number of communication buffers needed by a DRFPGA. These buffers are needed because the time-multiplexednature of DRFPGAs means that only a portion of the circuit implemented on the chip is present at any given time instance. Thus there is a need to store OT buffer signals until they are no longer needed. The hardware cost in a DRFPGA is the maximum number of buffers (plus associated routing) needed at any given time. We show experimentally that this number is almost as large as the number of computation nodes needed at any given time, and in some circuits twice as large. We also give a heuristic algorithm based on rescheduling nodes that reduces the number of buffers needed by 23%. Next we investigate time-multiplexed I/0 on a DRFPGA. We show that by using time-multiplexed 1/0pins, the number of physical I/0pins needed can be reduced by up to 83%.

On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution

Several industrial FPGA routing architectures have been shown to have no efficient routing algorithms (unless P=NP). Here, we further investigate if the intractability of the routing problem on a regular 2-D FPGA routing architecture can be alleviated by adding routing switches. We show that on this routing architecture, even with a substantial increase in switching flexibility, a polynomial time, predictable routing algorithm is still not likely to exist, and there is no constant ratio bound of the detailed over global routing channel densities. We also show that a perfect routing is unachievable on this architecture even with near complete (maximum) switching flexibility. We also discuss a new, greedy routing architecture, that possesses predictable and other desired routing properties, yet requires fewer routing resources than regular architectures. This theoretical result may suggest an alternative approach in routing architecture designs.

Not necessarily more switches more routability [sic.]

It has been observed experimentally that the mapping of global to detailed routing in a conventional FPGA routing architecture (2D array) yields unpredictable results. A different class of FPGA structures called greedy routing architectures (GRAs), where a locally optimal switch box routing can be extended to an optimal entire-chip routing, were investigated by Wu et al. (1994), Takashima et al. (1996) and Wu et al. (1996). It was shown that GRAs have good mapping properties. An H-tree GRA with W/sup 2/+2W switches per switch box (SpSB) and a 2D array GRA with 4W/sup 2/+2W SpSB were proposed by those authors (W is the number of tracks in each switch box). We continue this work by introducing an H-tree GRA with W/sup 2//2+2W SpSB and a 2D array GRA with 3.5 W/sup 2/+2 W SpSB. These new GRAs have the same good mapping properties but use fewer switches. We also show a class of FPGA architectures in which the mapping problem remains NP-complete, even with 6(W-1)/sup 2/+6W/sup 2/ SpSB (this is close to the maximum number of SpSB, which is 6W/sup 2/). Thus, more switches do not necessarily result in more routability.

Functional scan chain testing

Functional scan chains are scan chains that have scan paths through a circuits functional logic and flip-flops. Establishing functional scan paths by test point insertion (TPI) has been shown to be an effective technique to reduce the scan overhead. However once the scan chain is allowed to go through functional logic, the traditional alternating test sequence is no longer enough to ensure the correctness of the scan chain. We identify the faults that affect the functional scan chain, and show a methodology to find tests for these faults. Our results have the number of undetected faults at only 0.006% of the total number of faults, or 0.022% of the faults affecting the scan chain.

A flow based approach to the pin redistribution problem for multi-chip modules

Investigates the pin redistribution problem (PRP) for multi-chip modules. A novel transformation to the max-flow problem is introduced. This approach provides an efficient algorithm for finding a 2-layer solution, whenever one exists. A greedy heuristic to find a k-layer solution is described. The approach can find a minimum layer solution for two variants of the PRP; when each net can be routed on more than one layer, and when source and target terminals are drilled through all layers. Except for the heuristic procedure which takes O(km/sup 4/ log/sup 2/ m) time, the algorithms take O(/spl verbar/S/spl verbar/km/sup 2/) time, where S is the set of source terminals, m is the number of rows and columns in the grid, and k is the number of layers required. One can show that generalizations of the k-layer PRP are NP-complete problems.<<ETX>>

Time-multiplexed routing resources for FPGA design

We propose a time-multiplexed routing architecture for SRAM based FPGAs. This can be implemented by having two programmable SRAMs for each routing connection. The goal of this approach is to alleviate the on-chip routing bottleneck, and to increase the range of circuit sizes which can be accommodated on a single chip. We consider a Xilinx 4000 style architecture with and without time-multiplexed routing. Our experimental results show that time-multiplexed routing can reduce the channel density by 30%. Also, sharing permutation equivalent LUTs between the time phases can result in a 14% reduction of the number of LUTs required to implement a design.

A test synthesis approach to reducing BALLAST DFT overhead

In this paper, we present a test synthesis approach which integratesBALLAST (BALAnced structure Scan Test) withan enhanced test point insertion (TPI) algorithm to functionallyscan the flip-flops chosen by BALLAST.BALLASTis an attractive partial scan technique in that it offers combinationalATPG efficiency while promising to reduce full scanoverhead.However, the practical problem with BALLASTis it typically requires more scan flip-flops than other partialscan techniques.The TPI enhancements enable TPI toaim at the reduction of BALLAST overhead.The enhancementsinclude a more flexible test point insertion heuristic,a modified gain function which enables TPI to target a selectedset of flip-flops, and a more efficient procedure toremove redundant test points.The experimental results onnine benchmark circuits show the proposed test synthesisapproach can achieve on average 38% area saving comparedto full scan, while BALLAST alone achieves 17%.

PIN REDISTRIBUTION PROBLEM FOR MULTI-CHIP MODULES: ALGORITHMS AND COMPLEXITY

We investigate the pin redistribution problem (PRP) for multi-chip modules. We transform the PRP to the max-flow problem and obtain an efficient algorithm for finding a 2-layer solution, whenever one exists. A greedy heuristic to find a k-layer solution is described. Our approach can also construct a minimum layer solution for two variants; nets can be routed on more than one layer, and terminals (source and target) are drilled through all layers. Our algorithms take O(min{|S|, mk1/2}m2k) time, except for the heuristic procedure which takes O(km4log2 m) time, where S is the set of source terminals, m is the number of rows and columns in the grid, and k is the number of layers required. Several variations of the PRP when generalized to graphs can also be solved efficiently by our algorithms, whereas other variations are shown to be NP-complete.