Duan Zhikui

A fast transient response low dropout regulator with current control methodology

A transient performance optimized CCL-LDO regulator is proposed. In the CCL-LDO, the control method of the charge pump phase-locked loop is adopted. A current control loop has the feedback signal and reference current to be compared, and then a loop filter generates the gate voltage of the power MOSFET by integrating the error current. The CCL-LDO has the optimized damping coefficient and natural resonant frequency, while its output voltage can be sub-1-V and is not restricted by the reference voltage. With a 1 μF decoupling capacitor, the experimental results based on a 0.13 μm CMOS process show that the output voltage is 1.0 V; when the workload changes from 100 μA to 100 mA transiently, the stable dropout is 4.25 mV, the settling time is 8.2 μs and the undershoot is 5.11 mV; when the workload changes from 100 mA to 100 μA transiently, the stable dropout is 4.25 mV, the settling time is 23.3 μs and the overshoot is 6.21 mV. The PSRR value is more than −95 dB. Most of the attributes of the CCL-LDO are improved rapidly with a FOM value of 0.0097.

A novel dual-feed low-dropout regulator

A novel dual-feed (DF) low-dropout (LDO) is presented. The DF-LDO adopts dual control loops to maintain the output voltage. The dual control loops include a feedback loop and a feedforward loop. There is an equilibrium point in dual control loops, and the equilibrium point is the output voltage of the DF-LDO. In addition, the transient performance is optimized by adjusting the damping ratio and natural frequency. With a 1 μF decoupling capacitor, the proposed DF-LDO is fabricated in a 0.18 μm CMOS process and its output voltage is 1.5 V. When the workload changes from 100 μA to 100 mA in 100 ns, load regulation of 7 mV for a 100 mA step is achieved, the settling time is 997 ns and the undershoot is 12.8 mV; when the workload changes from 100 mA to 100 μA in 100 ns, the settling time is 249 ns with an imperceptible overshoot.