Tan Hongzhou

12 GHz wireless clock delivery using on-chip antennas: A case for future intra/inter-chip wireless interconnect

A wireless clock delivery technique using on-chip antennas is presented in this paper for future microprocessors. The realized system comprises a transmitter and several receivers integrated with on-chip antennas. The transmitter sends high frequency wireless clock by transmitting antenna which is picked up by receivers through receiving antennas. Simulations combining RF circuits with antennas are performed. The total chip area of transmitter and receiver including on-chip antennas and pads is 1 mm2 and 1.33 mm2, respectively. For a transmitter-receiver pair separated by 3 mm, the simulated peak-peak jitter of local clock is 6.8 ps. The performance of our wireless clock distribution is comparable with that of other novel clock distributions, which is even better in terms of jitter.

A novel dual-feed low-dropout regulator

A novel dual-feed (DF) low-dropout (LDO) is presented. The DF-LDO adopts dual control loops to maintain the output voltage. The dual control loops include a feedback loop and a feedforward loop. There is an equilibrium point in dual control loops, and the equilibrium point is the output voltage of the DF-LDO. In addition, the transient performance is optimized by adjusting the damping ratio and natural frequency. With a 1 μF decoupling capacitor, the proposed DF-LDO is fabricated in a 0.18 μm CMOS process and its output voltage is 1.5 V. When the workload changes from 100 μA to 100 mA in 100 ns, load regulation of 7 mV for a 100 mA step is achieved, the settling time is 997 ns and the undershoot is 12.8 mV; when the workload changes from 100 mA to 100 μA in 100 ns, the settling time is 249 ns with an imperceptible overshoot.

Effect of body biasing on single-event induced charge collection in deep N-well technology

As the device size decreases, the soft error induced by space ions is becoming a great concern for the reliability of integrated circuits (ICs). At present, the body biasing technique is widely used in highly scaled technologies. In the paper, using the three-dimensional technology computer-aided design (TCAD) simulation, we analyze the effect of the body biasing on the single-event charge collection in deep N-well technology. Our simulation results show that the body biasing mainly affects the behavior of the source, and the effect of body biasing on the charge collection for the nMOSFET and pMOSFET is quite different. For the nMOSFET, the RBB will increase the charge collection, while the FBB will reduce the charge collection. For the pMOSFET, the effect of RBB on the SET pulse width is small, while the FBB has an adverse effect. Moreover, the differenceof the effect of body biasing on the charge collection is compared in deep N-well and twin well.

Java processor VP6K applied in RFID systems

Radio Frequency Identification (RFID) is generic term for technology employing radio waves for detecting objects. RFID has wide application in payment systems, access control, asset tracking and other areas as many companies are using and developing the technologys potential. As RFID develops, it imports some new elements, one of which is Java technology. Java now can be seen in any links from RFID tags to database centre. But the performance of Java is still a main concern to us. This paper shows a good solution to deal with the efficiency problem when using Java technology in RFID systems. It firstly introduces advantages of Java processor. It can highly increase the performance of processing Java applications by implementing the technology in ASIC. After introducing some Java processors both for research and commercial, this paper leads us to the newly developed Java processor VP6K. Then details of functions and performance about the VP6K core and chip will be discussed. This paper also provides a hardware verifying platform for VP6K processor, in order to show cases of applications. Test results will be listed. In the end, this paper comes to the conclusion that VP6K is a high performance Java-specific processor, and further research plan will be made.

Blind and complete modeling of linear systems using third order cumulants

This paper presents a novel approach to structure determination of linear systems along with the choice of system orders and parameters. AutoRegressive (AR), Moving Average (MA) or AutoRegressive-Moving Average (ARMA) model structure can be extracted blindly from the Third Order Cumulants (TOC) of the system output measurements, where the unknown system is driven by an unobservable stationary independent identically distributed (i.i.d.) non-Gaussian signal. By means of the system order recursion, whether the system has an AR structure or has AR part of an ARMA structure is firstly investigated. MA features in the TOC domain is then applied as a threshold to decide if the system is an MA model or has MA part of an ARMA model. Numerical simulations illustrate the generality of the proposed blind structure identification methodology that may serve as a guideline for blind linear system modeling.