Dennis Ouma

Rapid characterization and modeling of pattern-dependent variation in chemical-mechanical polishing

Pattern-dependent effects are a key concern in chemical-mechanical polishing (CMP) processes. In oxide CMP, variation in the interlevel dielectric (ILD) thickness across each die and across the wafer can impact circuit performance and reduce yield. In this work, we present new test mask designs and associated measurement and analysis methods to efficiently characterize and model polishing behavior as a function of layout pattern factors-specifically area, pattern density, pitch, and perimeter/area effects. An important goal of this approach is rapid learning which requires rapid data collection. While the masks are applicable to a variety of CMP applications including back-end, shallow-trench, or damascene processes, in this study we focus on a typical interconnect oxide planarization process, and compare the pattern-dependent variation models for two different polishing pads. For the process and pads considered, we find that pattern density is a strongly dominant factor, while structure area, pitch, and perimeter/area (aspect ratio) play only a minor role.

An integrated characterization and modeling methodology for CMP dielectric planarization

Efficient chip-level CMP models are required to predict dielectric planarization performance for arbitrary layouts prior to CMP. We present an integrated calibration and modeling methodology for oxide planarization which extends previous work in several important ways. First, we describe improved characterization methods for model calibration, including new short flow test masks and simplified planarization model parameter extraction. Secondly, we present efficient physically motivated density calculation and integration with a planarization model for prediction of oxide thickness above and between metal structures across the entire die. Predictions based on the model show excellent agreement when applied to layouts not used in model calibration.

PATTERN DEPENDENT MODELING FOR CMP OPTIMIZATION AND CONTROL

In previous work, we have formalized the notions of “planarization length” and “planarization response function” as key parameters that characterize a given CMP consumable set and process. Once extracted through experiments using carefully designed characterization mask sets, these parameters can be used to predict polish performance in CMP for arbitrary product layouts. The methodology has proven effective at predicting oxide interlevel dielectric planarization results. In this work, we discuss extensions of layout pattern dependent CMP modeling. These improvements include integrated up and down area polish modeling; this is needed to account for both density dependent effects, and step height limits or step height perturbations on the density model. Second, we discuss applications of the model to process optimization, process control (e.g. feedback compensation of equipment drifts), and shallow trench isolation (STI) polish. Third, we propose a framework for the modeling of pattern dependent effects in copper CMP. The framework includes “removal rate diagrams” which concisely capture dishing height and step height dependencies in dual material polish processes.

Wafer Scale Variation of Planarization Length in Chemical Mechanical Polishing

Chemical mechanical polishing (CMP) has become the preferred planarization method for multilevel interconnect technology due to its ability to achieve a high degree of feature level planarity. However, methods are needed to understand and model both wafer level and die level uniformity in interlevel dielectric (oxide) polishing. This paper examines the variation of die level planarity across the wafer and at different process conditions. Substantial dependency of planarization length, a characteristic length which determines die level planarity, on table speed and down pressure is found, varying from 6.2 to 7.8 mm in the experiments considered here. In addition, a dependence of planarization length on die position within the wafer is found, varying by ∼0.5 mm across the wafer resulting in a difference of ∼300 A total indicated range from one die to the next. Some die are impacted even more strongly resulting in much smaller planarization lengths (near 5.0 mm in some cases) due to wafer edge effects. We conclude that accurate modeling and optimization of within-die variation depends on accurate modeling and measurement of not only wafer scale removal rate variation but also wafer scale planarization length variation.

Wafer-Scale Modeling of Pattern Effect in Oxide Chemical Mechanical Polishing

Dielectric film thickness variation arising from layout pattern dependency remains a major concern in oxide CMP. The severity of the pattern density effect is a function of the die location on the wafer, thus a combined wafer/die pattern dependent polishing model is required to fully assess the effectiveness of the process for a given planarization requirement. In this work, a two stage modeling methodology which accounts for both wafer-scale variation and within-die pattern dependencies, as well as their interaction, is developed. The effectiveness of the methodology is demonstrated over a range of polishing process conditions and consumable choices. We find that the integrated wafer/die CMP model accurately predicts the resulting increase or decrease in die-level pattern dependencies as a function of die position on the wafer.

A Novel Statistical Metrology Framework for Identifying Sources of Variation in Oxide Chemical‐Mechanical Polishing

A statistical metrology framework is used to identify systematic and random sources of interlevel dielectric thickness variation. Electrical and physical measurements, technology computer-aided design simulations, design of experiments, signal processing, and statistical analysis are integrated via statistical metrology to deconvolve interlevel dielectric thickness variation into constituent variation sources. In this way, insight into planarization variation is enabled; for a representative chemical/mechanical polishing process, we find that die-level neighborhood interactions are comparable to die level feature dependent effects, and that within each die, die level variation is greater than wafer level variation. The characterization of variation sources via statistical metrology is critical for improved process control, interconnect simulation, and robust circuit design.