Brian E. Stine

Logic characterization vehicle to determine process variation impact on yield and performance of digital circuits

Manufacturing of integrated circuits relies on the sequence of many hundred process steps. Each of these steps will have more or less variation, which has to be within a,certain limit to guarantee the chips functionality at a target speed. But, not every chip layout is susceptive to process variation the same way, which requires a link between process,capabilities and product design. This paper will present a novel Logic Characterization Vehicle (LCV) to investigate the yield and performance impact of process variation on high volume product chips. The LCV combines and manipulates new or already documented circuits like memory cells and combinatorial logic circuits within a JIG interface that allows fast and easy testability. Beside the functionality of such circuits, also path delay as well as cross talk issues can be determined. A standard digital functional tester can be used, since all timing critical measurements will be performed within the JIG. The described method allows early implementation of existing circuits for future technology nodes (shrinks). A Design Of Experiments (DOE) based implementation of possible layout manipulations will determine their impact on yield and performance of a target design as well as its sensitivity to process variation. The described approach can be used at a much earlier stage of product and process development, which will significantly shorten yield ramp.

Fast extraction of killer defect density and size distribution using a single layer short flow NEST structure

Defect inspection is required for process control and to enhance chip yield. Electrical measurements of test structures are commonly used to detect faults. To improve accuracy of electrically based determination of defect densities and defect size distributions, we present a novel NEST structure. There, many nested serpentine lines will be placed within a single layer only. This mask will be used as a short flow to guarantee a short turn around time for fast process data extraction. Data analysis procedures will provide densities and size distributions of killer defects that will have an impact on product chip yield.

On the impact of dishing in metal CMP processes on circuit performance

In this paper, we explore the impact of dishing in metal CMP processes on circuit performance. The impact on power distribution networks and clock distribution networks, critical components in modern VLSI designs, is of specific interest. For the two examples given in this paper, we find the impact to be very small.

Yield Improvement Using Fail Signature Detection Algorithm (FSDA)

An effective yield ramp methodology is demonstrated using fail signature detection algorithm (FSDA). Wafers with similar yield spatial patterns are grouped together to find stronger correlations to equipment data. Many signals that would have been missed otherwise were found leading to significant yield improvement

IC yield prediction and analysis using semi-empirical yield models and test data

This paper presents the result of an extension to the concept of Micro-Yield modeling. We have developed a design attribute extraction and yield prediction software system that - given the characterization of a semiconductor process via complex test chips that we call Characterization Vehicle test chips and IC product layout and a set of proprietary yield models - computes detailed contributions of different yield models, of geometrical chip regions and of parts of the chip circuitry to the overall chip yield. The organization of the computed output allows easy comparison of predicted yields to inspection and electrical test measurements, where the electrical tests can include failure bit maps for memories and scan tests results for logic circuits. After we review the concept of the Yield Impact Matrix, we define a more general Micro-Event paradigm and introduce the Extended YIMP. We discuss its application to yield loss root-cause analysis, review related work and present example applications of the overall system built around this concepts.

Innovative practices session 2C: Advanced in yield learning

The onset of FinFET technology nodes brings with it additional challenges in ramping yields due to new defect behaviors and new hardships in the physical failure analysis process. This presentation highlights these challenges and makes the argument that improved scan based diagnosis capabilities that leverage a transistor level understanding of the cells will be necessary to combat these challenges.

A system to translate product yield targets to equipment particle targets

Random defectivity reduction is an important prerequisite to achieving mature production yields. The typical technology roadmap includes a product yield / defect density reduction curve over the technology lifetime. Translating the defect density reduction curve into specific monthly targets for each individual module or for each single tool, has proven to be an extremely challenging task. This paper summarizes a proposed method to translate overall technology or product yield targets into corresponding defect density targets allocated to each tool. Achieving this task requires extensive characterization and modeling. This method was eventually used at a fab running 130 nm 6 metal layer copper process.

Yield Aware Equipment Preventive Maintenance (PM) Optimization

Typically equipment PM optimization and strategy is determined using a mix of various sources and inline inspection. In this work, the need for a more yield aware optimization strategy is recognized and recommendations made to implement this.