Duarte L. Oliveira

Continuous lipase-catalyzed production of fatty acid ethyl esters from soybean oil in compressed fluids.

This work investigates the continuous production of fatty acid ethyl esters from soybean oil in compressed fluids, namely carbon dioxide, propane and n-butane, using immobilized Novozym 435 as catalyst. The experiments were performed in a packed-bed bioreactor evaluating the effects of temperature in the range of 30-70 degrees C, from 50 to 150 bar, oil to ethanol molar ratio of 1:6-1:18 and solvent to substrates mass ratio of 4:1-10:1. In contrast to the use of carbon dioxide and n-butane, results showed that lipase-catalyzed alcoholysis in a continuous tubular reactor in compressed propane might be a potential route to biodiesel production as high reaction conversions were achieved at mild temperature (70 degrees C) and pressure (60 bar) conditions in short reaction times.

SUCCESSIVE CYCLES OF UTILIZATION OF NOVOZYM 435 IN THREE DIFFERENT REACTION SYSTEMS

The main focus of this work was to investigate the residual esterification activity and the product conversion after 10 successive cycles of utilization of a commercial lipase in three systems: esterification of 2-ethyl hexanol and palmitic acid in a solvent-free system; esterification of ascorbic acid and palmitic acid in tert-butanol; and transesterification of glycerol and methyl benzoate in 2-propanol. These systems were chosen based on previous results by our research group in terms of product conversion. Before scale-up, there is a need for evaluating several cycles of utilization of the biocatalyst. The esterification of 2-ethyl hexanol showed that after 10 cycles the enzyme retained 90% of its activity. The system consisting of ascorbic acid, palmitic acid, Novozym 435 and tert-butanol showed that a reduction in enzyme activity was accompanied by a reduction in reaction conversion; the same behavior was not observed for the third system.

Burst-Mode Asynchronous Controllers on FPGA

FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as burst mode, on FPGAs based on look-up table architectures. We present two conditions that, if satisfied, guarantee essential hazard-free implementation on any LUT-based FPGA. By doing that, besides all the intrinsic advantages of asynchronous over synchronous circuits, they also take advantage of the shorter design time and lower cost associated with FPGA designs.

SICARELO: A tool for synthesis of locally-clocked extended burst-mode asynchronous Controllers

Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of complex digital systems. These systems can present critical requirements, such as power consumption, robustness, speed, etc. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, but the lack of appropriate tools and the high difficulty of the design are already drawbacks. This paper proposes a new tool called SICARELO to automatic synthesis of asynchronous FSMs with local clock. The existence of a local clock reduces the requirements of asynchronous logic, enabling the synthesis in any PLD, such as CPLDs and FPGAs, without the need of satisfying any type of macro-cells mapping. The proposed tool starts from a popular specification known as Extended Burst Mode (XBM). The tool SICARELO was tested on a set of benchmarks, compared with 3D and Minimalist tools that are state of the art. SICARELO tool obtained a reduction media in the combinatorial logic of 32% of products and 25% of literals in the XBM_AFSM synthesis with local clock.

Design of locally-clocked asynchronous finite state machines using synchronous CAD tools

Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of embedded digital systems. These systems present critical requirements, such as power consumption, robustness, speed, etc. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, but the lack of appropriate tools and the high difficulty of the design are already drawbacks. This paper proposes a new method to design asynchronous FSM with local clock. The existence of a local clock reduces the requirements of asynchronous logic, enabling the synthesis in any PLD, such as CPLDs and FPGAs, without the need of satisfying any type of macro-cells mapping. Furthermore, when compared to other methods found in literature, it uses of conventional logic minimization tools that greatly facilitate the designing. The proposed method starts from a popular specification known as Extended Burst Mode (XBM) and uses a logic minimization synchronous tool for the synthesis. The achieved results show a high potential of practical implementation of this method for AFSM synthesis in PLDs.

Synthesis by direct mapping of asynchronous extended burst-mode controllers using RS latch

This paper proposes a new approach for synthesis by direct mapping of extended burst-mode asynchronous finite state machines (XBM_AFSM). The great advantage of the synthesis by direct mapping is the achieved simplicity in methodology, not demanding any knowledge about asynchronous logic concepts, hazard-free circuits and critical race theory. The synthesized XBM_AFSMs operate in mode Ib/Ob, which present superior performance when compared to generalized fundamental mode asynchronous circuits, once shows to be faster than those previously proposed in the literature and keeps a good modularity, provided by the simple interface with the external world. Starting from a well known extended burst-mode (XBM) specification, the direct mapping allows implementing large specifications with just little computational effort. The new approach uses the RS latch as memory element (cell control). A comparison is performed between three different memory elements from literature and the one proposed in this work. Comparing the latency time with the other three cells, it provided reductions from 7% to 22%, while comparing area, it showed to have an intermediate result between the others, being superior to some of them.

FPGA implementation of robust asynchronous wrappers for Globally-Asynchronous systems (GALS)

Contemporary digital systems must be based on the “System-on-Chip - SoC” concept. An interesting style for SoC design is the GALS paradigm (Globally Asynchronous, Locally Synchronous), which can be used to implement circuits in FPGAs (Field Programmable Gate Arrays), but the implementation of asynchronous interfaces (asynchronous wrapper - AW) constitutes a major drawback for this kind of devices. Although there is a typical AW design style which is based on asynchronous controllers and provides communication between modules (called ports), Port controllers are subject to essential-hazard when implemented FPGA. In this context, this paper proposes a new asynchronous GALS wrapper architecture to be implemented in FPGAs that is essentially free from hazard, not needing any special cares in implementation concerning to LUTs choice and being fully compatible with FPGA. Additional advantages of the proposed architecture are the total autonomy that synchronous modules achieve when interacting with the asynchronous wrapper; its ports can be synthesized in the direct mapping style (so without knowledge of asynchronous logic synthesis); and ports interacts in Ib/Ob Mode, not needing a timing analysis and also being more robust than GFM.

Using FPGAs to implement asynchronous pipelines

The asynchronous paradigm has interesting features due to the lack of the clock signal and it is another option for the project of digital systems. This paradigm has several design styles, where the micropipeline style is the most suitable one for FPGA platforms, due to the simplicity of its control. In this paper, we propose a pipeline architecture to implement asynchronous digital systems, in bundled-data micropipeline style, considering FPGAs as target devices. Through a case study, we show that the proposed architecture presents a 29% decrease in latency time and a 13% increase in throughput, compared with the state of the art architecture MOUSETRAP.

Synthesis of Low-Power Synchronous Controllers using FPGA Implementation

Today, a number of digital systems are described by an architecture consisting of a network of synchronous controllers and datapaths. These are battery-fed and may be implemented in VLSI technology and/or FPGAs (Field Programmable Gate Array). Since the batteries must have long life, reduction of energy consumption is the most important task in the design of such systems. In order to reduce dissipated power, a number of strategies have been suggested in the literature for both controllers and datapaths. In this article we suggest an approach that applies a new strategy for the synthesis of the low- consumption synchronous controllers. Our method synthesizes synchronous controllers that work at the two transition edges of clock signals, but only uses flip-flops that work at a single clock edge.

Implementation of Locally-Clocked XBM State Machines on FPGAs Using Synchronous CAD Tools

Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of complex digital systems. These systems can present serious problems related to the global clock. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, despite of the difficulties of the application of asynchronous logic. An interesting architecture for the Asynchronous Finite State Machines (AFSM) is based on local clock, because it reduces the requirements of asynchronous logic. This manuscript proposes a novel architecture of local clock for AFSMs, which is described by a popular specification known as Extended Burst-Mode (XBM). This architecture presents a better latency time when compared with other local clock architectures. Furthermore, the manuscript proposes a “necessary and sufficient” condition for local clock AFSMs to be synthesized completely on the proposed architecture by using only conventional tools. Through a case study, we present the architecture, its robustness, the synthesis procedure and a comparison with other local clock architectures, highlighting its advantages.