Tiago Curtinhas

SICARELO: A tool for synthesis of locally-clocked extended burst-mode asynchronous Controllers

Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of complex digital systems. These systems can present critical requirements, such as power consumption, robustness, speed, etc. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, but the lack of appropriate tools and the high difficulty of the design are already drawbacks. This paper proposes a new tool called SICARELO to automatic synthesis of asynchronous FSMs with local clock. The existence of a local clock reduces the requirements of asynchronous logic, enabling the synthesis in any PLD, such as CPLDs and FPGAs, without the need of satisfying any type of macro-cells mapping. The proposed tool starts from a popular specification known as Extended Burst Mode (XBM). The tool SICARELO was tested on a set of benchmarks, compared with 3D and Minimalist tools that are state of the art. SICARELO tool obtained a reduction media in the combinatorial logic of 32% of products and 25% of literals in the XBM_AFSM synthesis with local clock.

Design of locally-clocked asynchronous finite state machines using synchronous CAD tools

Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of embedded digital systems. These systems present critical requirements, such as power consumption, robustness, speed, etc. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, but the lack of appropriate tools and the high difficulty of the design are already drawbacks. This paper proposes a new method to design asynchronous FSM with local clock. The existence of a local clock reduces the requirements of asynchronous logic, enabling the synthesis in any PLD, such as CPLDs and FPGAs, without the need of satisfying any type of macro-cells mapping. Furthermore, when compared to other methods found in literature, it uses of conventional logic minimization tools that greatly facilitate the designing. The proposed method starts from a popular specification known as Extended Burst Mode (XBM) and uses a logic minimization synchronous tool for the synthesis. The achieved results show a high potential of practical implementation of this method for AFSM synthesis in PLDs.

Implementation of Locally-Clocked XBM State Machines on FPGAs Using Synchronous CAD Tools

Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of complex digital systems. These systems can present serious problems related to the global clock. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, despite of the difficulties of the application of asynchronous logic. An interesting architecture for the Asynchronous Finite State Machines (AFSM) is based on local clock, because it reduces the requirements of asynchronous logic. This manuscript proposes a novel architecture of local clock for AFSMs, which is described by a popular specification known as Extended Burst-Mode (XBM). This architecture presents a better latency time when compared with other local clock architectures. Furthermore, the manuscript proposes a “necessary and sufficient” condition for local clock AFSMs to be synthesized completely on the proposed architecture by using only conventional tools. Through a case study, we present the architecture, its robustness, the synthesis procedure and a comparison with other local clock architectures, highlighting its advantages.

A novel asynchronous interface with pausible clock for partitioned synchronous modules

Contemporary digital systems must necessarily be based on the “System-on-Chip - SoC” concept. An interesting style for SoC design is GALS (Globally Asynchronous, Locally Synchronous) paradigm. Currently, the major drawback in the design of a GALS system shows to be the asynchronous interface (asynchronous wrapper - AW), especially when the GALS system is applied to a multi-point topology. The AW interfaces found in literature are always based on controller ports. They are responsible for data communication between locally synchronous modules, where to each point of data communication there is an input or output port. The increasing number of port leads to complex AWs and to a high increase in area. This paper proposes a new asynchronous GALS interface focused on multi-point GALS. For a case study considering a multi-point data communication system, the proposed interface achieved an average reduction in area (products + literals) of 85% and 74%, when compared to two different AWs found in literature.

A novel Κ convention logic (NCL) gates architecture based on basic gates

Digital circuit design may demand critical requirements, such as power consumption, robustness, performance, etc., while being implemented in VLSI (Very Large Scale Integration). The asynchronous paradigm presents interesting features that serve as an alternative to these critical requirements. An important class of the asynchronous paradigm is the one called QDI (Quasi Delay Insensitive) circuits that can also be used for critical requirements design. QDI circuits are interesting for these applications because they are robust to certain kinds of faults, to noise and to temperature and supply voltage variations, having also low electromagnetic emissions. An interesting style of QDI circuits is the NCL (Κ Convention Logic) circuits because they accept conventional Boolean functions and can achieve great optimization. This paper presents an architecture based on basic QDI gates for the synthesis of NCL gates focusing on VLSI that uses only standard libraries and FPGA (Field Programmable Gate Array).

State assignment of direct output synchronous FSMs using genetic algorithm

Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the design of digital hardware and that can be implemented in Field Programmable Gate Arrays (FPGAs). A class little known and very interesting of SFSM in the FPGA platform is the SFSMs of direct output (SFSM_DO). These state machines use the output signals as state signals, thus allowing several advantages when compared to conventional SFSM classes. Of these advantages, we can mention: elimination of glitches in the output signals; reduction of the number of state variables; reduction in latency time. This paper proposes an algorithm for state assignment using a genetic algorithm that introduces a minimum number of state variables. The proposed method was applied in twelve known benchmarks and showed a significant average reduction of 145.0%, 70.0%, 47.1% and 67.1% in the number of state variables, number of products, number of literals and area (LUTs + FFs), respectively, when compared the one-hot encoding.

Robust architecture for locally-clocked extended burst-mode circuits without timing assumption

Asynchronous controllers based on Asynchronous Finite State Machines (AFSM) are widely used in the control unit design of asynchronous systems. These systems can be implemented in Field Programmable Gate Arrays (FPGAs), which are a low cost design alternative. Different styles have been proposed to implement AFSMs, but all of them have limitations when implemented in FPGAs. Therefore, this paper proposes a novel architecture for AFSMs in the local clock style. AFSMs are described in the extended burst-mode (XBM) specification. The existence of a local clock reduces the requirements of asynchronous logic, but the timing requirements may require the insertion of delays, which makes FPGA implementation difficult and leads to degradation of performance and reliability. The novel proposed local clock architecture is robust to setup and hold time violations, so they are free of timing analysis and do not need to introduce any kind of delays. The proposed architecture was applied to thirteen benchmarks and when compared to the local clock architecture of SICARELO tool, focused on FPGAs, it did not need to introduce any delays, whereas SICARELO had to introduce delays in all thirteen benchmarks of up to 4.9ns and there was an average reduction of 30% at the time of latency.

Design of low-power two-hot finite state machines operating on double-edge clock

Synchronous controllers are finite state machines (FSM) that utilize flip-flop memory elements to store states and the clock signal to synchronize their operations. In a digital system, the activity of the clock is a major source of energy dissipation. It is responsible for 15% to 45% of the total consumed energy. Reducing the activity of the clock leads to a reduction of the total energy. An interesting strategy is designing the digital system to operate on both edges of the clock (double-edge triggered — DET), therefore allowing a 50% reduction in the frequency of the clock with the same processing rate. Synchronous FSMs, when encoded in one-hot style, also present interesting properties, but with the disadvantage of increasing the number of flip-flops and leading to higher power consumption. In this paper we propose a new method for the synthesis of synchronous FSMs that are encoded in two-hot style. The synthesized synchronous FSMs operate in both edges of the clock, therefore operating at half frequency. Although operating in both edges of the clock, only conventional flip-flops, which are sensitive to a single edge of the clock signal (single-edge transition flip-flops — SET-FF), are used. Then, although the code is two-hot, state transitions occur in the one-hot style, therefore keeping all the properties of this style.

Design of gated-clock asynchronous wrappers for multi-point GALS systems

An interesting style for SoC (Systems-on-Chip) circuit design is the GALS (Globally Asynchronous, Locally Synchronous) paradigm, but its major drawback shows to be the asynchronous interfaces, especially when the GALS system is applied to a multi-point topology. The asynchronous interfaces found in literature are based on port controllers and can be called asynchronous wrappers (AW). They are responsible for data communication between locally synchronous modules, where, to each point of data communication, there is an input or an output port. The increasing number of ports leads to complex AWs and to a high increase in area. This paper proposes a new asynchronous interface focused on multi-point GALS. In a case study, considering a multi-point data communication system, the proposed interface achieved an average reduction of 33% and 41% in latency times, when compared to two different AWs found in literature.

Automatic synthesis of locally-clocked extended burst-mode AFSMs based on transparent latches

Summary form only given. Controllers based on Synchronous Finite State Machines (SFSM) are components widely used in complex digital systems. These systems can present critical requirements, such as power consumption, robustness, performance, etc. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, but the lack of appropriate tools and the high difficulty of the design are already drawbacks. This paper proposes a new architecture, based in transparent latches, for implementing asynchronous FSMs with local clock. The existence of a local clock reduces the requirements of asynchronous logic. The asynchronous FSMs with local clock, implemented in the new architecture, are synthesized by SICARELO method. This method parts from a popular specification known as extended burst-mode (XBM) and uses the techniques of the synchronous paradigm to accomplish the synthesis. The new architecture was tested in a set of well-known benchmarks and compared with the AFSMs implemented through the standard architecture gRS, synthesized by the Miriã tool. Compared to Miriã tool, SICARELO tool achieved an average reduction of 12% in the number of state variables, 4% in the combinatorial logic of products and 15% in literals, although presenting a penalty of 79% on the number of latches. These results lead to a high potential of practical implementation of this method in actual applications.