Leonardo Romano

SICARELO: A tool for synthesis of locally-clocked extended burst-mode asynchronous Controllers

Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of complex digital systems. These systems can present critical requirements, such as power consumption, robustness, speed, etc. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, but the lack of appropriate tools and the high difficulty of the design are already drawbacks. This paper proposes a new tool called SICARELO to automatic synthesis of asynchronous FSMs with local clock. The existence of a local clock reduces the requirements of asynchronous logic, enabling the synthesis in any PLD, such as CPLDs and FPGAs, without the need of satisfying any type of macro-cells mapping. The proposed tool starts from a popular specification known as Extended Burst Mode (XBM). The tool SICARELO was tested on a set of benchmarks, compared with 3D and Minimalist tools that are state of the art. SICARELO tool obtained a reduction media in the combinatorial logic of 32% of products and 25% of literals in the XBM_AFSM synthesis with local clock.

Synthesis of Low-Power Synchronous Controllers using FPGA Implementation

Today, a number of digital systems are described by an architecture consisting of a network of synchronous controllers and datapaths. These are battery-fed and may be implemented in VLSI technology and/or FPGAs (Field Programmable Gate Array). Since the batteries must have long life, reduction of energy consumption is the most important task in the design of such systems. In order to reduce dissipated power, a number of strategies have been suggested in the literature for both controllers and datapaths. In this article we suggest an approach that applies a new strategy for the synthesis of the low- consumption synchronous controllers. Our method synthesizes synchronous controllers that work at the two transition edges of clock signals, but only uses flip-flops that work at a single clock edge.

Synthesis of synchronous digital systems operating in double-edge of clock

In a synchronous digital system the activity of the clock signal is a major consumer of energy. It consumes 15% to 45% of energy consumed. Reducing the activity of the clock signal produces a reduction of energy considered, but also reduces clock skew problems and iteration electromagnetic. An interesting strategy is the synchronous digital system to operate in the transitions of both edges of the clock signal (double-edge triggered - DET), as this allows a 50% reduction in the frequency of the clock signal, but having the same processing rate data. In this paper we propose a method for synthesis of synchronous digital systems that operate on both edges of the clock signal, but the state memory is composed only of flip-flops that are sensitive to a single edge of the clock signal (single-edge triggered flip-flops - SET-FF).

A novel asynchronous interface with pausible clock for partitioned synchronous modules

Contemporary digital systems must necessarily be based on the “System-on-Chip - SoC” concept. An interesting style for SoC design is GALS (Globally Asynchronous, Locally Synchronous) paradigm. Currently, the major drawback in the design of a GALS system shows to be the asynchronous interface (asynchronous wrapper - AW), especially when the GALS system is applied to a multi-point topology. The AW interfaces found in literature are always based on controller ports. They are responsible for data communication between locally synchronous modules, where to each point of data communication there is an input or output port. The increasing number of port leads to complex AWs and to a high increase in area. This paper proposes a new asynchronous GALS interface focused on multi-point GALS. For a case study considering a multi-point data communication system, the proposed interface achieved an average reduction in area (products + literals) of 85% and 74%, when compared to two different AWs found in literature.

A synchronous wrapper for high-speed heterogeneous systems on FPGAs

Taking advantage of synchronous and asynchronous paradigms, a new style of design, called Globally Synchronous Locally Asynchronous (GSLA), has achieved very interesting results. In this paper, we propose a synchronous wrapper that allows the communication of “synchronous to asynchronous to synchronous” modules. Internally, the proposed interface comprises an asynchronous module. The GSLA design style is interesting for Field-Programmable Gate Array (FPGA) platforms because it facilitates the design of Application Specific Integrated Circuits (ASIC). Through two case studies, the “differential equation solver” and the “FIR Filter”, we show that the proposed synchronous wrapper presents a reduction of up to 27% in the processing time and an increase of up to 747% in the global clock rate when compared with the synchronous design.

Design of low-power two-hot finite state machines operating on double-edge clock

Synchronous controllers are finite state machines (FSM) that utilize flip-flop memory elements to store states and the clock signal to synchronize their operations. In a digital system, the activity of the clock is a major source of energy dissipation. It is responsible for 15% to 45% of the total consumed energy. Reducing the activity of the clock leads to a reduction of the total energy. An interesting strategy is designing the digital system to operate on both edges of the clock (double-edge triggered — DET), therefore allowing a 50% reduction in the frequency of the clock with the same processing rate. Synchronous FSMs, when encoded in one-hot style, also present interesting properties, but with the disadvantage of increasing the number of flip-flops and leading to higher power consumption. In this paper we propose a new method for the synthesis of synchronous FSMs that are encoded in two-hot style. The synthesized synchronous FSMs operate in both edges of the clock, therefore operating at half frequency. Although operating in both edges of the clock, only conventional flip-flops, which are sensitive to a single edge of the clock signal (single-edge transition flip-flops — SET-FF), are used. Then, although the code is two-hot, state transitions occur in the one-hot style, therefore keeping all the properties of this style.

Design of gated-clock asynchronous wrappers for multi-point GALS systems

An interesting style for SoC (Systems-on-Chip) circuit design is the GALS (Globally Asynchronous, Locally Synchronous) paradigm, but its major drawback shows to be the asynchronous interfaces, especially when the GALS system is applied to a multi-point topology. The asynchronous interfaces found in literature are based on port controllers and can be called asynchronous wrappers (AW). They are responsible for data communication between locally synchronous modules, where, to each point of data communication, there is an input or an output port. The increasing number of ports leads to complex AWs and to a high increase in area. This paper proposes a new asynchronous interface focused on multi-point GALS. In a case study, considering a multi-point data communication system, the proposed interface achieved an average reduction of 33% and 41% in latency times, when compared to two different AWs found in literature.

Automatic synthesis of locally-clocked extended burst-mode AFSMs based on transparent latches

Summary form only given. Controllers based on Synchronous Finite State Machines (SFSM) are components widely used in complex digital systems. These systems can present critical requirements, such as power consumption, robustness, performance, etc. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, but the lack of appropriate tools and the high difficulty of the design are already drawbacks. This paper proposes a new architecture, based in transparent latches, for implementing asynchronous FSMs with local clock. The existence of a local clock reduces the requirements of asynchronous logic. The asynchronous FSMs with local clock, implemented in the new architecture, are synthesized by SICARELO method. This method parts from a popular specification known as extended burst-mode (XBM) and uses the techniques of the synchronous paradigm to accomplish the synthesis. The new architecture was tested in a set of well-known benchmarks and compared with the AFSMs implemented through the standard architecture gRS, synthesized by the Miriã tool. Compared to Miriã tool, SICARELO tool achieved an average reduction of 12% in the number of state variables, 4% in the combinatorial logic of products and 15% in literals, although presenting a penalty of 79% on the number of latches. These results lead to a high potential of practical implementation of this method in actual applications.

Design of synchronous pipeline digital systems operating in double-edge of the clock

In contemporaneous digital systems the fetch by performance is critical, many times is accomplished through of the use of the pipeline control. In these systems the activity of the clock signal is a major energy consumer. It is responsible for 15% to 45% of the total consumed energy. Once reducing the activity of the clock signal, it is possible not only a reduction of the considered energy, but also a reduction of clock skew problems and electromagnetic iteration. An interesting strategy to achieve this goal is to design the synchronous digital system to operate in transitions of both edges of the clock signal (double-edge triggered - DET), once it allows a 50% reduction in the frequency of the clock signal, although showing the same processing rate data. In this paper it is proposed a method that synthesizes synchronous digital systems with pipeline control that operate on both edges of the clock signal, using only flip-flops sensitive to a single edge of the clock signal (single-edge triggered flip-flops-SET-FF) as components of the state memory. The proposed method presents very good potential to reduce the problems associated with the clock, has a high probability of practical implementation with low penalty on area.

FPGA implementation of asynchronous controllers from generalized multi-burst graph specification

FPGAs have been mainly used for designing of synchronous controllers. However, it is difficult to design asynchronous controllers on them because the circuit may suffer from hazard problems. This paper presents a method that implements a class of asynchronous controllers on FPGAs which are based on Look-Up Table (LUT) architectures. Asynchronous controllers specification used in heterogeneous (synchronous +asynchronous) systems rely on two types of signals: level sensitive signals that are used as conditionals and transition sensitive signals. Another requirement is to describe concurrency between inputs/outputs. The Multi-Burst Graph (MBG) specification allows to described these controllers in a compact form and also the MBG specification is familiar to the designers of digital circuits. This paper also proposes a generalization in the MBG specification to increase the ability to describe the interaction between inputs/ outputs. Our method begins from Generalized MBG specification. By doing this, the asynchronous circuits besides their intrinsic advantages over synchronous ones may also take advantage of integration, lower costs and short-time design associated with FPGA designs.