Lester de Abreu Faria

SICARELO: A tool for synthesis of locally-clocked extended burst-mode asynchronous Controllers

Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of complex digital systems. These systems can present critical requirements, such as power consumption, robustness, speed, etc. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, but the lack of appropriate tools and the high difficulty of the design are already drawbacks. This paper proposes a new tool called SICARELO to automatic synthesis of asynchronous FSMs with local clock. The existence of a local clock reduces the requirements of asynchronous logic, enabling the synthesis in any PLD, such as CPLDs and FPGAs, without the need of satisfying any type of macro-cells mapping. The proposed tool starts from a popular specification known as Extended Burst Mode (XBM). The tool SICARELO was tested on a set of benchmarks, compared with 3D and Minimalist tools that are state of the art. SICARELO tool obtained a reduction media in the combinatorial logic of 32% of products and 25% of literals in the XBM_AFSM synthesis with local clock.

Design of locally-clocked asynchronous finite state machines using synchronous CAD tools

Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of embedded digital systems. These systems present critical requirements, such as power consumption, robustness, speed, etc. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, but the lack of appropriate tools and the high difficulty of the design are already drawbacks. This paper proposes a new method to design asynchronous FSM with local clock. The existence of a local clock reduces the requirements of asynchronous logic, enabling the synthesis in any PLD, such as CPLDs and FPGAs, without the need of satisfying any type of macro-cells mapping. Furthermore, when compared to other methods found in literature, it uses of conventional logic minimization tools that greatly facilitate the designing. The proposed method starts from a popular specification known as Extended Burst Mode (XBM) and uses a logic minimization synchronous tool for the synthesis. The achieved results show a high potential of practical implementation of this method for AFSM synthesis in PLDs.

Synthesis by direct mapping of asynchronous extended burst-mode controllers using RS latch

This paper proposes a new approach for synthesis by direct mapping of extended burst-mode asynchronous finite state machines (XBM_AFSM). The great advantage of the synthesis by direct mapping is the achieved simplicity in methodology, not demanding any knowledge about asynchronous logic concepts, hazard-free circuits and critical race theory. The synthesized XBM_AFSMs operate in mode Ib/Ob, which present superior performance when compared to generalized fundamental mode asynchronous circuits, once shows to be faster than those previously proposed in the literature and keeps a good modularity, provided by the simple interface with the external world. Starting from a well known extended burst-mode (XBM) specification, the direct mapping allows implementing large specifications with just little computational effort. The new approach uses the RS latch as memory element (cell control). A comparison is performed between three different memory elements from literature and the one proposed in this work. Comparing the latency time with the other three cells, it provided reductions from 7% to 22%, while comparing area, it showed to have an intermediate result between the others, being superior to some of them.

FPGA implementation of robust asynchronous wrappers for Globally-Asynchronous systems (GALS)

Contemporary digital systems must be based on the “System-on-Chip - SoC” concept. An interesting style for SoC design is the GALS paradigm (Globally Asynchronous, Locally Synchronous), which can be used to implement circuits in FPGAs (Field Programmable Gate Arrays), but the implementation of asynchronous interfaces (asynchronous wrapper - AW) constitutes a major drawback for this kind of devices. Although there is a typical AW design style which is based on asynchronous controllers and provides communication between modules (called ports), Port controllers are subject to essential-hazard when implemented FPGA. In this context, this paper proposes a new asynchronous GALS wrapper architecture to be implemented in FPGAs that is essentially free from hazard, not needing any special cares in implementation concerning to LUTs choice and being fully compatible with FPGA. Additional advantages of the proposed architecture are the total autonomy that synchronous modules achieve when interacting with the asynchronous wrapper; its ports can be synthesized in the direct mapping style (so without knowledge of asynchronous logic synthesis); and ports interacts in Ib/Ob Mode, not needing a timing analysis and also being more robust than GFM.

Implementation of Locally-Clocked XBM State Machines on FPGAs Using Synchronous CAD Tools

Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of complex digital systems. These systems can present serious problems related to the global clock. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, despite of the difficulties of the application of asynchronous logic. An interesting architecture for the Asynchronous Finite State Machines (AFSM) is based on local clock, because it reduces the requirements of asynchronous logic. This manuscript proposes a novel architecture of local clock for AFSMs, which is described by a popular specification known as Extended Burst-Mode (XBM). This architecture presents a better latency time when compared with other local clock architectures. Furthermore, the manuscript proposes a “necessary and sufficient” condition for local clock AFSMs to be synthesized completely on the proposed architecture by using only conventional tools. Through a case study, we present the architecture, its robustness, the synthesis procedure and a comparison with other local clock architectures, highlighting its advantages.

A novel asynchronous interface with pausible clock for partitioned synchronous modules

Contemporary digital systems must necessarily be based on the “System-on-Chip - SoC” concept. An interesting style for SoC design is GALS (Globally Asynchronous, Locally Synchronous) paradigm. Currently, the major drawback in the design of a GALS system shows to be the asynchronous interface (asynchronous wrapper - AW), especially when the GALS system is applied to a multi-point topology. The AW interfaces found in literature are always based on controller ports. They are responsible for data communication between locally synchronous modules, where to each point of data communication there is an input or output port. The increasing number of port leads to complex AWs and to a high increase in area. This paper proposes a new asynchronous GALS interface focused on multi-point GALS. For a case study considering a multi-point data communication system, the proposed interface achieved an average reduction in area (products + literals) of 85% and 74%, when compared to two different AWs found in literature.

Prototyping and characterization of a QWIP-FPA ROIC Unit Cell

A Quantum-Well Infrared Photodetector Focal Plane Array Read-Out Integrated Circuit Unit Cell (QWIP-FPA ROIC unit cell) is prototyped and characterized. The implemented architecture was the source-follower direct injection (SFDI) which presents high linearity, reduced area and high integration time capability. Details of its behavior, as well as secondary effects, are discussed from the experimental results. Concepts like frequency variation, charge injection, clockfeedthrough, dynamic range and switching time delays are presented and discussed. It is shown that this Unit Cell behavior is in accordance with the theoretical concepts and indicates a great potential to be practically implemented in bigger FPA ROICs.

A novel fully-programmable analog fuzzifier architecture for interval type-2 fuzzy controllers using current steering mirrors

A novel analog fuzzy membership function generator architecture, based on current steering mirrors, for interval type-2 fuzzy controllers is proposed in this paper. The Footprint of Uncertainty (FOU), characteristic of an interval type-2 fuzzy set, is generated by this novel architecture, which uses current steering mirrors controlled by a voltage input and allows width variation based on a central line. This main feature makes the circuit inherently type-2, i.e., not dependent of any type-1 fuzzifier, unlike all previous analog fuzzifiers found in the literature. The circuit operates in current mode and is capable of generating trapezoidal, triangular, Z-shaped and S-shaped membership functions. Input currents allow shape configuration, whereas a digitally programmable current mirror provides different inclinations, making it fully programmable (shape, width of the FOU, inclination, and position). Simulations validating the architecture were performed with TSMC CMOS 0.18 m technology, in CADENCE software. The circuit was later fabricated and characterized. Experimental results confirmed its ability to work as a fuzzifier, with all specified features, showing to be suitable even for dedicated low power applications. 11

A novel Κ convention logic (NCL) gates architecture based on basic gates

Digital circuit design may demand critical requirements, such as power consumption, robustness, performance, etc., while being implemented in VLSI (Very Large Scale Integration). The asynchronous paradigm presents interesting features that serve as an alternative to these critical requirements. An important class of the asynchronous paradigm is the one called QDI (Quasi Delay Insensitive) circuits that can also be used for critical requirements design. QDI circuits are interesting for these applications because they are robust to certain kinds of faults, to noise and to temperature and supply voltage variations, having also low electromagnetic emissions. An interesting style of QDI circuits is the NCL (Κ Convention Logic) circuits because they accept conventional Boolean functions and can achieve great optimization. This paper presents an architecture based on basic QDI gates for the synthesis of NCL gates focusing on VLSI that uses only standard libraries and FPGA (Field Programmable Gate Array).

Robust architecture for locally-clocked extended burst-mode circuits without timing assumption

Asynchronous controllers based on Asynchronous Finite State Machines (AFSM) are widely used in the control unit design of asynchronous systems. These systems can be implemented in Field Programmable Gate Arrays (FPGAs), which are a low cost design alternative. Different styles have been proposed to implement AFSMs, but all of them have limitations when implemented in FPGAs. Therefore, this paper proposes a novel architecture for AFSMs in the local clock style. AFSMs are described in the extended burst-mode (XBM) specification. The existence of a local clock reduces the requirements of asynchronous logic, but the timing requirements may require the insertion of delays, which makes FPGA implementation difficult and leads to degradation of performance and reliability. The novel proposed local clock architecture is robust to setup and hold time violations, so they are free of timing analysis and do not need to introduce any kind of delays. The proposed architecture was applied to thirteen benchmarks and when compared to the local clock architecture of SICARELO tool, focused on FPGAs, it did not need to introduce any delays, whereas SICARELO had to introduce delays in all thirteen benchmarks of up to 4.9ns and there was an average reduction of 30% at the time of latency.