Dudley Augustus Chance

A Ceramic Capacitor Substrate for High Speed Switching VLSI Chips

An integrated capacitor substrate which is proposed as an essential part in the realization of a thin film module for high speed digital computing systems is discussed. Several innovative multilayer ceramic (MLC) concepts relative to the fabrication of the desired low inductance capacitor and current paths to chips are described. Ceramic and metal composite material sets which may be used in the fabrication are also proposed. Experimental evaluations of some of the crucial concepts were made and included in the discussions. The result is an elegant approach to the fabrication of one of the key requirements in realizing the thin film high performance module.

Refractory metallization of green ceramic

Successful refractory metallization of green ceramic is shown to require close matching of the shrinkages of the metal layer and the ceramic substate. Selection of specific metal particle sizes is used as the prime controlling parameter for metallizing several alumina ceramic types, including commercially pure alumina. Warpage of the fired part and adhesion of the metallization are demonstrated to be dependent on and controllable by the choice of metal particle distribution. Properly selected particle distribution results in flat metallized ceramic parts and good adhesion is obtained with pure elemental particles; other additives are unnecessary. X-ray stress analysis data and warpage results are correlated with pull strength measurements.

Metal-ceramic constraints for multilayer electronic packages

Ceramic formulations set in an organic binder are currently being cast in thin paper-like sheets. These sheets may be punched, screened with metal pastes, and laminated to form a composite of metal and ceramic particles held together by an organic medium. By slowly burning off the organic binder and then sintering the ceramic and metal together, a substrate with many layers of interconnecting wiring may be obtained. The coincident sintering of the ceramic and metal phases presents compatibility constraints. Temperature considerations with respect to shrinkage and coefficient of expansion match between the ceramic and metal phases as well as solid/solid and solid/ambient interactions are important constraints in the fabrication of these composites. High conductivity metals (e.g., Ag, Cu) are generally not available for co-firing because sintering temperatures of important ceramic formulations are higher than the melting points of these metals. This constraint has been minimized through the use of capillary infiltration of molten metals into the ceramic structure. Consequently, it is now possible for multilayer ceramic structures to provide the interconnection wiring densities and conductivities necessary to respond to the needs of greater circuit densities of integrated circuit chips. Material selections are reviewed on the basis of electrical properties, ambient interactions, stresses due to sintering shrinkage, and thermal coefficient of expansion. Certain problems, tradeoffs, and procedures used in the fabrication of a multilayer substrate with Cu-filtrated lines are discussed.

Capillary-infiltrated conductors in ceramics

The infiltration of high conductivity metals into capillaries in ceramic structures have been reported by Schwartz and Wilcox. Others have used the infiltration concept for the fabrication of composite structures for a variety of reasons, thermal expansions, machinability of hard metals, and so forth. In electronic applications, that is the fabrication of ceramic structures for support and interconnection of devices, the reasons for infiltration are evident. They provide highly conductive paths in a controlled manner for dimensions and configurations which approach those of device structures. Experiments were conducted to investigate the wetting and spreading of copper on molybdenum metallized alumina slips. Various surface-active and viscosity-active metals were added to the copper, and ambient conditions were varied. The results indicate that the primary controlling parameters for wetting are the ambient conditions. The infiltrations of copper into porous molybdenum lines were observed by X-radiographs of experimental substrates after increments of time at 1120°C. The substrates were moved from an average temperature of 1040°C into a hot zone at 1120°C, then after an incremental soak time were returned to 1040°C, and subsequently cooled for observation. The penetrations of copper are clearly seen on the X-radiographs so that the process of infiltration may be closely monitored. The results indicate that reliable infiltrations at predictable rates may be obtained. Thus, the technique is a reliable means of achieving high conductivity metals within a ceramic substrate. There is no indication of a limitation on penetration distance on well formed lines as small as 5 mil wide. Electrical conductivity of infiltrated lines was observed to follow the volume relationship: Σ=vCuΣCu + vMoΣMo where Σ = conductivity andv = volume proportion.

Theory of pressure sintering of glass ceramic multichip carriers

A method of pressure sintering multilayer glass ceramic packages (MLC) that results in a hermetic product is described. Use of this process results in a reduced process time, and is achieved without the use of a die, which is commonly employed during pressure sintering. Complex glass ceramic multichip substrates have been sintered this way to produce products with a flat edge contour and minimal distortion of the internal vias. In this article, we present a model that provides the fundamental basis for the pressure sintering approach to processing MLC. In this semi-quantitative model, the mechanism of pressure sintering, i.e., the process of dimensional changes, is controlled by viscous flow induced by sintering, and lamination flow created by an applied pressure. The pressure sintering model is capable of predicting the flow, density, and dimensional changes of a glass ceramic carrier during pressure sintering in the absence of a die. Both the temperature and pressure schedules are time dependent, and the pressure can vary over a range from zero, corresponding to free sintering, to large pressures (up to at least 800 psi) that closely simulate experimental data.

Glass-passivated GaAs chip tunnel diode

A novel approach to the fabrication of tunnel diodes is described. The experimental tunnel diode is a gallium arsenide planar device, using a conventional alloyed junction in an epitaxially grown GaAs substrate, and hermetically sealed by a high-temperature glass coating. The tunnel diode is fused to a circuit module using a solder reflow method. This package provides a high degree of mechanical reliability, great reduction in size, and an easy means of interconnection. Another unique feature is that the peak current is tailored electrically to within 1% by altering the impurity distribution near the junction, rather than by the conventional electrochemical etching technique. The resulting gallium arsenide tunnel diodes, having peak currents of 8 mA and capacitances of 5 pF, are suitable for use in a one-nanosecond switching circuit.