Durodami J. Lisk

Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs

Reducing interconnect delay and power consumption has become a major concern in deep submicron designs. 3-D technologies have been proposed as a promising solution to mitigate interconnect problems. This paper examines the electrical characterization of vertical intertier connections such as through silicon via (TSV) and microbumps considering process variations and studies their timing impact on the circuit level. We first provide parasitic RC characteristics of intertier connections including TSV and microbumps and examine their delay. Then circuit simulation is performed to evaluate the timing impact of intertier connections.

Power and signal integrity challenges in 3D systems

Power/signal delivering network for 2D systems comprising a package and an Integrated Circuit (IC) are design tasks that can be concurrently handled today. Design iterations can be locally carried out in each subsystem part without the need to modify the other ones decisions. This is unfortunately not the case in 2.5D/3D stacked systems. Finer system integration technology, either via Through Silicon Stack (TSS) and/or Through Silicon Interposer (TSI), involves tighter evaluation of the coupling effects in the system-wide PDN impedance and Signal Integrity (SI) characteristics. If these interactions are not properly accounted early in the design cycle, undesired design loop iterations, affecting design productivity is possible. Therefore, new tools and flows incorporating abstracted physical information of the PDN and signal interconnect stack architecture are needed for early design exploration. This paper elaborates on the problems, tool flows and methods necessary to address these challenges for 2.5D/3D stacked systems.

3D stacking: Where the rubber meets the road

Summary form only given. A 2.5D/3D multi die interposer with TSV (Through Silicon Via) allows massive wide parallel busses between memory and logics devices, improves speed, and significantly reduces power consumption. The TSV and silicon interposer are amongst the most promising technologies that offer the greatest vertical interconnects density. This new establishment will change the semiconductor industry paradigm for many years to come. 2.5D/3D technology introduces a new degree of electrical design complexity which is unfamiliar to many existing electrical design methodologies and EDA tools. A new electrical verification methodology must be developed with consideration to the micro level (TSV and interposer structures) and macro/system level simulation. At the Micro level, modeling of TSV is challenging due to its dependency on the material properties of the medium surrounding it and its impact on the signal losses/attenuation, capacitance effects, and the coupling among the vertical interconnects. At the Macro level, new electrical characteristics of the system need to be closely coupled with the thermal and mechanical tolerances of the entire 2.5D/3D packaging structure in order for its ultra wideband data exchange between logic chip and memory chips. TSV placement on logic and memory chips must be carefully placed during the chip design placement stage in order to avoid unnecessary electromagnetic coupling and faulty logic latching. Traditional separate signal and power integrity analysis methodologies are no longer sufficient due to the close proximity of the power and signal distribution network. In order to accurately predict the performance of 2.5D/3D packages, a new design paradigm shift is needed to toggle 2.5D/3D system performance optimization. New design and modeling approaches along with new breeds of computational electroma