Dyi-Chung Hu

Embedded glass interposer for heterogeneous multi-chip integration

Interposer technology has been developed for providing a fine line/space and high density interconnections that cannot be matched by current laminate substrate technology. Interposer materials such as silicon, glass and organic had been under intensive development. We have been developing EIC (Embedded Interposer Carrier) technology which eliminates the interconnection between the interposer and the underneath organic substrate [1, 2]. This could provide a lower profile, good electrical performance, and do not change the current industry infrastructure. Besides silicon, there are various advantages in using glass as interposer; such as low loss characteristic in high frequency, high degree of flatness for fine line patterning and adjustable CTE to lower the stress of heterogeneous package structure. Moreover, the potential of producing glass interposer in large panel format enables glass interposer to be more cost effective solution comparing to Silicon interposer. In this study, an EIC substrate with embedded glass interposer for flip chip assembly is demonstrated. Glass interposers with size of 21×14 mm2 and 100 μm thickness, through glass vias (TGV) of 30 μm diameter, and line/space of 3 μm/3 μm were produced. Subsequently, the glass interposer was embedded in built-up dielectric materials to form the EIC substrate. Multi-layers dielectrics were built up with filled blind vias and RDL patterns to fan-out the circuits from the embedded glass interposer. The production of EIC was conducted in a 508 mm×508 mm panel using standard printed circuit board production line. Later, special designed Si chips to mimic the AP (application processor, 2,904 I/O in 9×9 mm2) and wide I/O chips (1,200 I/Os in 10×10 mm2) were flip-chip bonded to the EIC substrate via joints of 40 μm pitch Cu pillars and micro solder bump to form an integrated module.

20″ × 20″ panel size glass substrate manufacturing for 2.5D SiP application

For high density interconnection IC packages of the future, the outlook is for thinner packages with higher routing densities. With that, managing the substrate warpage along processing steps becomes critical. Thin organic substrates face challenging warpage issues in manufacture and in chip assembly. Glass is one of the candidates that can be used in substrate to replace traditional organic substrate. The infrastructure of glass for LCD industry has already been developed for many years. Glass also has several superior properties than other substrate candidates, such as large panel size availability, adjustable CTE, high modulus, low dielectric constant, low dielectric loss and high insulating capability. Glass represents an attractive choice with potential of tailorable properties dependent on specific glass composition. By targeting the coefficient of thermal expansion (CTE), the CTE of glass can be made to match perfectly with silicon dies and for reliable package. In addition, the advantages of using glass for interposer derive from process flexibility for size and thickness since the glass fusion process provides sheets with dimensions of more than three meters. It is straight forward to provide glass substrate of almost any size needed. Large glass panels are ideally suited for fabrication of interposer where the panel process is expected to provide large number of interposers in each run compared with wafer processing. In addition, the two sided processing of the panel, the avoidance of CMP processes and without using liners further enable lower unit cost for the interposer. This paper demonstrates fabrication of glass interposer with through glass vias (TGV) daisy chain test vehicles using a 20” x 20” (508mm x 508mm) panel size glass substrate manufactured by substrate HVM (high volume manufacture) line for 2.5D SiP application. Daisy chain electrical measurement results of this glass substrate demonstrated good continuity and electric resistance. The reliability test results will also be described including pre-condition and thermal cycle test (TCT).

An innovative embedded interposer carrier for high density interconnection

It is well known that 3DIC integration is the next generation semiconductor technology with the advantages of small form factor, high performance and low power consumption. However the device TSV process and design rules are not mature. Assembly the chips on top of the Si interposer is the current most desirable method to achieve the requirement of good performance. In this study, a new packaging concept, the Embedded Interposer Carrier (EIC) technology was developed. It aims to solve some of the problems facing current interposer assemble issues. It eliminates the joining process of silicon interposer to the laminate carrier substrate. The concept of EIC is to embed one or multiple interposer chips into the build-up dielectric layers in the laminated substrate. The process development of EIC structure is investigated in this paper. EIC technology not only can shrink an electronic package and system size but also provide a better electronic performance for high-bandwidth applications. EIC technology can be one of the potential solutions for 3D System-in-Package.

Ultra-thin line embedded substrate manufacturing for 2.1D/2.5D SiP application

For high density interconnection IC packages of the future, the outlook is for thinner packages with higher routing densities. With that, fine line substrate technology becomes critical. Current organic substrates are limited to line/space larger than 8/8 μm for by conventional semi-additive plating (SAP) technology. It may have yield loss issue due to weak adhesion of line/space less than 5/5 μm, especially in long distance line. But the impact of weak adhesion of fine line is very small in line embedded (LE) substrate because of it is in embedded structure. Line embedded is made by laser patterning of dielectric. Dry film material, chemicals for lithography like developer, and stripper are not needed. The circuits are embedded, and capable of stereo copper features. It can cover FC, CSP, CIS, coreless structures. Line embedded technology can provide better electric performance with lower variation of trench width/depth. It can form fine pitch trench line/space less than 5/5 μm. It also has better design flexibility & reliability than SAP process. In this paper, we will discuss the key of the processes and demonstrate the fabrication of fine line substrate in the coreless process of build-up 5/5 μm line/space by adopting line embedded technology. Line embedded was made by laser direct ablation (LDA) on organic build-up dielectric material. By using core as carrier and build-up dielectric material with finer filler size, the coreless structure has demonstrated lower warpage and good trench capability. Laser ablation process capability also shows excellent trench depth control. In order to get better copper thickness uniformity, novel uniform Cu plating technology on trench, pad, and via has development. Low cost and uniform Cu reduction process was also evaluated and developed. We also evaluated the feasibility of separation after molding. Different types of molding compounds are evaluated and good flatness material is found.

Embed glass interposer to substrate for high density interconnection

Current organic substrates are limited to lines/space 10/10 μm and via size around 50 μm. However, the semiconductor with advance node needs fine line/space of 5/5 or 3/3 and even 2/2 μm in the future. Interposer provides a high density interconnection with fine line and small via that cannot be matched by current laminate substrate technology. We have proposed a new structure that embedded interposer to organic substrate (Flip chip - Embedded Interposer Carrier, FC-EIC®). This structure has virtues of know good substrate and compatible with current packaging and assembly infrastructure. We have demonstrated the feasibility of integrating silicon interposer to a laminate substrate. In this paper, we evaluated the feasibility of integration of a glass interposer into an organic substrate. The selection of glass, temporary bonding materials and built-up dielectric materials were established. The compatibility of lamination and built-up process with glass interposer was demonstrated. By using dielectric materials with small CTE and high modules together with an innovative structure, significant warpage reduction of the EIC-glass was achieved. For a 10 cm × 10 cm laminated carrier with a proper dielectric material set, the panel warpage of the EIC-glass structure can be reduced from 20 mm to less than 3 mm. The EIC-glass structure has been tested under 500 TCT cycles and no glass damage and delamination between glass and the built-up dielectric film was observed.