Ra-Min Tain

Cooling performance of silicon-based thermoelectric device on high power LED

In this paper, a new thermal management application of silicon-based thermoelectric (TE) device on high power LED is unveiled. The silicon-based TE device is fabricated by the microfabrication and flip-chip assembly process. Thermal images photographed by infrared camera demonstrate the cooling function of the silicon-based TE devices. Because the LED chip is encapsulated in a package, the junction temperature of the LED chip cannot be measured directly. An electrical-thermal conversion method is used to measure the junction temperature of the high power LED. The result shows that the silicon-based thermoelectric device can effectively reduce the thermal resistance of the high power LED.

Thermal evaluation and analyses of 3D IC integration SiP with TSVs for network system applications

In this study, we used simulation technique to analyze the thermal behaviors and investigate the thermal issues of a designed system in package (SiP) for network system application that based on a three dimensional integrated circuit (3D IC) structure. The 3D IC SiP has an interposer which with regularly embedded through-silicon vias (TSVs); there are one CPU chip and two DRAM chips planted on the top side and bottom side of the interposer, respectively. The interposer with chips is bonded on a BT substrate; the BT substrate is bonded on a PCB; and a metallic heat spreader is placed on and glued to the CPU chips back-side. Because a 3D IC SiP with TSVs is so complicate for modeling and very difficult for meshing, this study attempted to use the equivalent models of embedded TSV, bump/solder bond and metallic trace to simplify a detail 3D IC model. We introduced a slice model, that four stacked chips on an interposer and each chip has two heaters and TSVs, to verify the accuracy and feasibility of the equivalent model by comparing to the detail model, the results of both models show that they are in a good agreement. By using the equivalent model to simulate the studied 3D IC integrated SiP; we found the CPU temperature would be dominated by the cooling capability of a thermal module that attached on the heat spreader. As for the DRAM chips that underneath the interposer, it is inevitable to have a quite high temperature due to the temperature superposition effect and an obstructed heat flow path. In fact, the severely high temperature of the chips under an interposer should be the main thermal issue for such a 3D IC SiP because there is no easy thermal solution for these chips.

Energy release rate investigation for through silicon vias (TSVs) in 3D IC integration

The technology of 3D IC integration is highly probable to achieve the demand for high performance, better reliability, miniaturization and lower-priced portable electronic products. Since the through silicon via (TSV) is the heart in 3D IC integration architectures, the reliability issues of TSV interconnects should be extremely concerned. Due to the large thermal expansion mismatch among the Cu, Si, and SiO2, the induced thermal stresses and strains can occur and become the driving forces for failures in TSV interconnects. Hence, the stress analyses and failure mode investigation for TSVs are in urgent need. Among the typical failures, the mostly common failure type is delamination, which will be caused when lower energy release rate (ERR) or higher critical stresses at interfaces are presented. In this study, the finite element modeling (FEM) for a symmetrical single in-line copper filled TSV with redistribution layer is illustrated. Two kinds of horizontal cracks that embedded in the interface of SiO2 passivation and Cu seed layer (Cu pad delamination cases) are introduced to realize the interfacial ERR, where is also the critical stress area that observed from finite element analysis. The significance of design parameters such as crack length, TSV diameter, TSV pitch, depth of TSV, SiO2 thickness and Cu seed layer thickness are also brought up. The methodology of design of experiments (DoE) has been adopted to capture the most important mechanical parameters of the TSV to comprehend the corresponding ERR. It is believed that these results would be helpful to avoid delamination of TSV interconnects in 3D IC integration.

Estimation for equivalent thermal conductivity of silicon-through vias TSVs used for 3D IC integration

In this study, thermal performance of 3D IC integration is investigated. Emphasis is placed on the determination of a set of equivalent thermal conductivity equations for Cu-filled TSVs with various TSV diameters, TSV pitches, TSV thicknesses, passivation thicknesses, and microbump pads. Also, a slice model to imitate a 3D memory stacked chip is adopted to verify the accuracy of the equivalent equations. Finally, the feasibility of these equivalent equations is demonstrated through a simple 3D IC integration structure.

Through-Silicon Hole Interposers for 3-D IC Integration

In this investigation, a system-in-package (SiP) that consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top and bottom sides (a real 3-D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top chip, bottom chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be performed to demonstrate the integrity of the SiP structure.

Ultra low-cost through-silicon holes (TSHs) interposers for 3D IC integration SiPs

In this study, a very low-cost silicon interposer with many through-silicon holes (TSHs) for 3D IC integration system-in-package (SiP) applications is proposed. Unlike TSVs (through-silicon vias), the uniqueness of this design is there is not the dielectric layer, barrier layer, seed layer, filled Cu, and thus CMP and TSV Cu reveal are not necessary for the TSHs. The vertical interconnects between (face-to-face) the top chips and bottom chips of the TSH interposer are through Cu wires or columns. The electrical, thermal and mechanical behaviors of this new design are demonstrated by nonlinear finite element simulations.

Embedded glass interposer for heterogeneous multi-chip integration

Interposer technology has been developed for providing a fine line/space and high density interconnections that cannot be matched by current laminate substrate technology. Interposer materials such as silicon, glass and organic had been under intensive development. We have been developing EIC (Embedded Interposer Carrier) technology which eliminates the interconnection between the interposer and the underneath organic substrate [1, 2]. This could provide a lower profile, good electrical performance, and do not change the current industry infrastructure. Besides silicon, there are various advantages in using glass as interposer; such as low loss characteristic in high frequency, high degree of flatness for fine line patterning and adjustable CTE to lower the stress of heterogeneous package structure. Moreover, the potential of producing glass interposer in large panel format enables glass interposer to be more cost effective solution comparing to Silicon interposer. In this study, an EIC substrate with embedded glass interposer for flip chip assembly is demonstrated. Glass interposers with size of 21×14 mm2 and 100 μm thickness, through glass vias (TGV) of 30 μm diameter, and line/space of 3 μm/3 μm were produced. Subsequently, the glass interposer was embedded in built-up dielectric materials to form the EIC substrate. Multi-layers dielectrics were built up with filled blind vias and RDL patterns to fan-out the circuits from the embedded glass interposer. The production of EIC was conducted in a 508 mm×508 mm panel using standard printed circuit board production line. Later, special designed Si chips to mimic the AP (application processor, 2,904 I/O in 9×9 mm2) and wide I/O chips (1,200 I/Os in 10×10 mm2) were flip-chip bonded to the EIC substrate via joints of 40 μm pitch Cu pillars and micro solder bump to form an integrated module.

Low-cost TSH (through-silicon hole) interposers for 3D IC integration

In this investigation, a SiP (system-in-package) which consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top- and bottom-side (a real 3D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top-chip, bottom-chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be preformed to demonstrate the integrity of the SiP structure.

Nonlinear thermal stress analyses and design guidelines for through silicon vias (TSVs) in 3D IC integration

In this investigation, a set of empirical equations which predicts the maximum thermal stresses at the vicinity of a copper filled TSV for 3D IC integration has been proposed. The finite element model of a symmetrical single in-line TSV with redistribution layer has been created at first and the parametric study includes the TSV diameter, pitch, and thickness, and the thickness of SiO2 passivation and Cu seed layer. The methodology of design of experiments (DOE) has been adopted to deliver a set of empirical equations which captures the most important mechanical parameters of TSVs to comprehend the corresponding thermal stress and strain responses. Through this set of empirical equations, the estimated maximum thermal stresses and strains for different TSV diameter (from 10μm to 50μm) can be explained and the significant geometrical parameters can be easily observed. In addition, based on the present parametric study and results, a set of design guidelines for optimizing the mechanical performance of copper filled TSV in 3D IC integration has been proposed. These results are helpful to engineers if thermal stress solutions for TSVs in 3D IC integration are required.

Non-refrigerant thermoelectric air conditioning technique on vehicles

An electrical compressor technique of thermoelectric (TE) based climate control system in passenger vehicles provides solid state design and construction, non-refrigerants and the ability of providing faster time to comfort, beltless solution that enables engine-off air conditioner operation and modified the adversely impact by belt-driven vapor compression air conditioners, improved efficiency of positive temperature coefficient (PTC) heater systems. A complete scale TE air conditioning module was designed and adjusted to appropriate performance with CAE analyzing approaches, the well designed module proceeded practically constructed and tested on vehicle system to validate the design concept. In the design, system integration and energy management algorithms have been improved to further increase system level efficiency. To analyze the COP and cooling ability of the TE vehicle cooling system, a mathematical model is proposed, and a robust control algorithm is applied. The test results are presented and discussed.