E. Josse

A Cost-Effective Low Power Platform for the 45-nm Technology Node

This paper presents a cost-effective 45-nm technology platform, primarily designed to serve the wireless multimedia and consumer electronics needs. This platform features low power transistors operating at a nominal voltage of 1.1V, an ultra low k dielectric (k~2.5) with up to 9 Cu metal layers and 0.25/0.3/0.37mum2 SRAM cells. This platform also features an optional third gate oxide for either higher speed or active power mitigation. This technology has been developed on the (100)-oriented substrate with a key focus on process simplicity. Transistor improvement relies on mask-free strain engineering techniques along with co-implanted halos and laser anneal. The impact of laser anneal on transistor reliability and mixed-signal capabilities are also examined. Drive current as high as 660/320 muA/mum at 1nA/mum and 1.1V are reported

Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology

In this paper, we present FD-SOI with High-K and Single Metal gate as a possible candidate for LP multimedia technology. Dual gate oxide co-integrated devices with EOT 17Å/Vdd 1.1V and 29Å/Vdd 1.8V are reported. The interest of Ultra-Thin Buried Oxide substrates (UTBOX) is reported in term of Multiple Vt achievement and matching improvement. Delay improvement up to 15% is reported on Ring Oscillators as compared to bulk 45nm devices. In addition, for the first time 99.998% 2Mbit 0.374µm2 SRAM cut functionality has been demonstrated. Thanks to a hybrid FDSOI/bulk co-integration with UTBOX all IPs required in a SOC are demonstrated for LP applications.

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

We report FDSOI devices with a 20nm gate length (L_G) and 5nm spacer, featuring a 20% tensile strained Silicon-on-Insulator (sSOI) channel NFET and 35% [Ge] partially compressive strained SiGe-on-Insulator (SGOI) channel PFET. This work represents the first demonstration of strain reversal of sSOI by SiGe in short channel devices. At V_dd of 0.75V, competitive effective current (I_eff) reaches 550/340 μA/μm for NFET, at I_off of 100/1 nA/μm, respectively. With a fully strained 30% SGOI channel on thin BOX (20nm) substrate and V_dd of 0.75V, PFET I_eff reaches 495/260 μA/μm, at I_off of 100/1 nA/μm, respectively. Competitive sub-threshold slope and DIBL are reported. With the demonstrated advanced strain techniques and short channel performance, FDSOI devices can be extended for both high performance and low power applications to the 10nm node.

Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs

We fabricated Fully-Depleted (FD) nMOSFETs on strain-SOI substrates (sSOI), exceeding regular FDSOI devices by +20% in nMOS ON-state current (ION) and +18% in SRAM read current. For pMOSFETs on sSOI, the integration of Si0.57Ge0.43 by the Ge-enrichment technique (in so-called sSGOI) is the solution to reach the performance of Si0.78Ge0.22 channels built on SOI (SGOI) in terms of short channel hole mobility and ION. We analyse the layout effects in sSOI/sSGOI transistors, ring oscillators (ROs) and SRAMs for different Ge amounts and strains and report for the first time the carrier mobility in sSOI/sSGOI vs. the active length (Lac). Through a layout optimization, a high uniaxial strain can be created, boosting the carrier mobility in both sSOI/sSGOI by 10/20% and ensuring the scalability of the planar FDSOI architecture for the 10nm node.

Impact of Source–Drain Series Resistance on Drain Current Mismatch in Advanced Fully Depleted SOI n-MOSFETs

In this letter, we demonstrate the existence of the source-drain series resistance mismatch and its impact on drain current variability with regard to the other mismatch parameters. To this end, we propose a new methodology for the drain current mismatch study based on Y-function, enabling a precise determination of the various variability sources in advanced fully depleted silicon on insulator (SOI) MOS devices.

Full front and back split C-V characterization of CMOS devices from 14nm node FDSOI technology

In this paper, a full front and back split C-V characterization of FDSOI devices and associated methodology to accurately extract the EOT (Equivalent oxide thickness) of the front and back (BOX) oxide as well as the channel thickness are presented for the first time.

A new technique to extract the gate bias dependent s/d series resistance of sub-100nm MOSFETs

In this study, a new technique to extract the S/D series resistance (R<inf>sd</inf>) from the total resistance versus transconductance gain plot R<inf>tot</inf>(1/β) is proposed. The technique only requires the measurement of I<inf>d</inf>(V<inf>gs</inf>)|<inf>Vgt</inf> and β, allowing fast and statistical analysis in an industrial context. Unlike the usual R<inf>tot</inf>(L)-based techniques, it has the advantage of being insensitive to the channel length and mobility variations and finally enables to extract very accurate values for R<inf>sd</inf>(V<inf>gs</inf>) and the effective mobility reduction factor µ<inf>eff</inf>(V<inf>gt</inf>)/µ<inf>eff</inf>(0).

Design / technology co-optimization of strain-induced layout effects in 14nm UTBB-FDSOI CMOS: Enablement and assessment of continuous-RX designs

We report on the main local layout effect in 14nm Ultra-Thin Buried oxide and Body Fully Depleted Silicon On Insulator (UTBB-FDSOI) CMOS technology [1]. This effect is demonstrated by Nano-Beam Diffraction to be directly induced by the strain in the SiGe channel and reproduced by an accurate electrical compact model. An original continuous-RX design optimizes the stress management, maintaining longitudinal stress component while relaxing the transverse one. A 28% ring oscillator delay improvement is experimentally demonstrated at same leakage for 1-finger inverter at VDD=0.8V supply voltage and a frequency gain up to 15% is simulated in a critical path of an A9 core.

Experimental and Theoretical Investigation of Magnetoresistance From Linear Regime to Saturation in 14-nm FD-SOI MOS Devices

The feasibility of geometric magnetoresistance (MR) measurement from linear to saturation operation regime is demonstrated in ultrathin body and BOX fully depleted silicon-on-insulator devices from 14-nm technology node. Besides, we propose a new physical compact model for MOSFET drain current under high field transport, which reproduces experimental MR mobility from linear to saturation operation region and serves as the basis for a new extraction method of carrier saturation velocity. A benchmarking with state-of-the-art saturation velocity extraction methodologies is also conducted. Our saturation velocity results indicate that, for this technology, nonstationary transport prevails as manifested by an overshoot velocity behavior, still far from the ballistic limit.

New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs

A thorough investigation and statistical analysis of the low-frequency (LFN) and random telegraph noise (RTN) in 28 and 14nm FD-SOI CMOS transistors is presented, for the first time. It is shown that the 14nm technology node is improved in terms of threshold voltage fluctuations when compared to the 28nm one. A new analysis method that directly probes the RTN presence is also proposed. Finally, the LFN/RTN impact on the device dynamic variability is presented through CADENCE design suite circuit simulations.