S. Haendler

28nm FDSOI technology platform for high-speed low-voltage digital applications

For the first time, a full platform using FDSOI technology is presented. This work demonstrates 32% and 84% speed boost at 1.0V and 0.6V respectively, without adding process complexity compared to standard bulk technology. We show how memory access time can be significantly reduced thanks to high Iread, by keeping competitive leakage values. Yield of ~14Mb SRAM cells is demonstrated, allowing to measure for the first time Vmin of SRAM arrays.

Low-Frequency Noise Investigation and Noise Variability Analysis in High-

Low-frequency noise (LFN) of high-k/metal stack nMOS and pMOS transistors is experimentally studied. Results obtained on 32-nm complementary metal-oxide-semiconductor (CMOS) technologies, including LFN spectra and normalized power spectral density data analysis, are presented. These results indicate that the carrier number fluctuation is the main noise source for both nMOS and pMOS devices. As noise performance may strongly vary between different devices on one chip, the variability of the LFN when scaling down devices was also evaluated. A model known in the literature was used and enhanced in order to understand the noise level variability. A statistical analysis of the noise variability is also presented showing the dependence of the standard deviation with the device area. The comparison with former results from 45-nm poly/SiON technology demonstrates a better control of noise variability in the 32-nm CMOS technology.

k

This paper presents the superior performance of UTBB (Ultra-Thin Box and Body) technology for providing high speed at low voltage. We evidence the transistor capability to sustain full forward-body-biasing solution thanks to a planar back-side gate scheme. Silicon measurements on low complexity circuits show that the dynamic power consumption can be reduced by 90% without any speed degradation by simply selecting the appropriate power supply and body bias couple (Vdd; Vbb). A simple switching energy efficiency model is then proposed allowing the (Vdd; Vbb) couple prediction reaching the minimum energy point. Finally, we demonstrate on a full CPU Core implementation with UTBB a total power reduction of -30% and a +40% energy efficiency at identical speed with respect to bulk technology thanks to back side gate biasing efficiency.

/Metal Gate 32-nm CMOS Transistors

In this paper, we present FD-SOI with High-K and Single Metal gate as a possible candidate for LP multimedia technology. Dual gate oxide co-integrated devices with EOT 17Å/Vdd 1.1V and 29Å/Vdd 1.8V are reported. The interest of Ultra-Thin Buried Oxide substrates (UTBOX) is reported in term of Multiple Vt achievement and matching improvement. Delay improvement up to 15% is reported on Ring Oscillators as compared to bulk 45nm devices. In addition, for the first time 99.998% 2Mbit 0.374µm2 SRAM cut functionality has been demonstrated. Thanks to a hybrid FDSOI/bulk co-integration with UTBOX all IPs required in a SOC are demonstrated for LP applications.

Switching energy efficiency optimization for advanced CPU thanks to UTBB technology

In this paper, we present, for the first time, a thorough investigation of low frequency noise (LFN) and statistical noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors. The experimental results are well interpreted by Monte-Carlo LFN simulations based on the random spatial and energy distribution of discrete traps in the gate dielectric. Our results clearly indicate that the LFN variability of 28nm FD-SOI CMOS technology is improved as compared to previous 45nm and 32nm bulk CMOS technologies.

Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology

In this paper we compare Fully-Depleted SOI (FDSOI) devices with different BOX thicknesses with or without ground plane (GP). With a simple High-k/Metal gate structure, the 32 nm devices exhibits Ion/Ioff performances well situated for low power (LP) applications. The different BOX thicknesses and ground plane conditions are compared with bulk shrunk technology in terms of variability and noise. 0.499 mum2 SRAM cell has been characterized with less than 50 pA of standby current/cell and a SNM of 210 mV @ Vdd 1V.

Low frequency noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors

In this letter, we demonstrate the existence of the source-drain series resistance mismatch and its impact on drain current variability with regard to the other mismatch parameters. To this end, we propose a new methodology for the drain current mismatch study based on Y-function, enabling a precise determination of the various variability sources in advanced fully depleted silicon on insulator (SOI) MOS devices.

FDSOI devices with thin BOX and ground plane integration for 32nm node and below

In this paper, the low-frequency excess noise due to the kink effect in deep submicron unibond N-metal oxide semiconductor field effect transistor (N-MOSFETs) is investigated. Drain current power spectral density measurements are performed for partially and moderately fully depleted and body-tied devices. The behavior of this effect with the frequency is thoroughly analysed and the control of such a noise overshoot by applying a back-gate voltage is also demonstrated and discussed. A comparison between unibond and SIMOX technologies, in terms of noise behavior, is presented. Finally, the impact of the body contact on the noise is also shown.

Impact of Source–Drain Series Resistance on Drain Current Mismatch in Advanced Fully Depleted SOI n-MOSFETs

In this study, we present recent low frequency noise results obtained on Si/SiGeC Heterojunction Bipolar Transistors (HBTs) associated with a 0.13μm BiCMOS technology. Two technologies are studied, referenced as A and B, with high frequency figures of merit f_T/f_MAX (unity current gain frequency/maximum oscillation frequency) 220/280 GHz for technology A and 300/400 GHz for technology B. The LF Noise measurements are performed in the 1Hz-100 kHz frequency range as a function of the base bias current and of the emitter area A_E. The 1/f noise component is studied through the SPICE LFN parameters A_F and K_F. The K_B figure of merit (K_B = K_F *A_E), used to compare the 1/f noise level, has an excellent value of 1.5 10^-10 μm² for technology A and above 6 10^-10 μm² for technology B. Dispersion of the 1/f noise level observed on technology B is associated to the presence of predominant GR components. A temperature study of the 1/f noise level evolution in the range 15-100°C was also done. The temperature dependence is week except at very low base current bias.

Kink-Related Excess Noise in Deep Submicron Partially and Moderately Fully Depleted Unibond N-Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

Low-frequency (LF) noise has been studied on 28 nm FDSOI devices with ultra-thin silicon film (7 nm) and thin buried oxide (25 nm). A strong dependence of the noise level on the combination of the front and back biasing voltages was observed, and justified by the coupling effect of both Si/High-K dielectric and Si/SiO2 interface noise sources (channel/front oxide and channel/buried oxide), combined with the change of the Remote Coulomb scattering. From comparisons of the experimental and simulation results, it is shown that the main reason of this dependence is the distance of the charge distribution centroid from the interfaces, which is controlled by both front and back-gate bias voltages, and the way this distance affects the Remote Coulomb scattering coefficient a. A new LF noise model approach is proposed to include all these effects. This also allows us to assess the oxide trap density values for both interfaces.