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Featured researches published by M. Haond.


Solid-state Electronics | 1995

Impact of LDD structures on the operation of silicon MOSFETs at low temperature

I. M. Hafez; G. Ghibaudo; F. Balestra; M. Haond

Abstract The impact of Lightly Doped Drain structures (LDD) on the electrical characteristics of Si MOS transistors is investigated from liquid helium up to room temperature. It is found that the presence of LDD regions strongly alters the ohmic drain current characteristics at low temperatures ( ≤ 100 K). This feature is attributed to the increase of the source-drain series resistance due to the impurity freeze-out which takes place in the LDD regions. In contrast, it is also found that, for sufficiently high drain and gate voltages, the drain current is only weakly affected by the presence of LDDs. The analysis of the drain current and output conductance characteristics allows us to demonstrate that the LDD resistance is indeed a non-linear function of the longitudinal electric field. The above LDD resistance dependence with electric field is interpreted in term of field assisted impurity ionization which occurs in the LDD regions. The mechanisms responsible for the field assisted impurity ionization are discussed with regard to the Poole-Frenkel effect and the shallow level impact ionization process. Moreover, a simple model for the field dependent LDD resistance is proposed and makes it possible to explain quantitatively the change of the output conductance with temperature for MOS devices operated at low and very low temperatures.


Microelectronic Engineering | 1995

Improved hot-carrier immunity of p-MOSFETs with 8nm thick nitrided gate-oxide during bi-directional stressing

A. Bravaix; Dominique Vuillaume; D. Goguenheim; D. Dorval; M. Haond

Abstract The hot-carrier reliability in p + poly-gate p-MOSFETs with pure and nitrided 8nm thick gate-oxide is investigated under uniform and localized electron injections. The effects of bidirectionally DC-(AC) stressing on the saturated (linear) - mode transistor parameters are monitored as they represent the worst limitating factor in pass transistors for digital logic applications. With a proper RTA condition and nitridation ambient, it is found that the gate-oxide process obtained by low-pressure plasma nitridation shows better hot-carrier immunity than pure oxide with a significant reduction of charge trapping.


european solid state device research conference | 1994

Channel Engineering by Heavy Ion Implants

Thomas Skotnicki; L. Guerin; D. Mathiot; M. Gauneau; A. Grouillet; C. D'Anterroches; E. Andre; P. Bouillon; M. Haond


device research conference | 2010

A Plasma NH 3 Process to Improve the Reliability of 0.35μm P + Poly-Gate Nitrided Oxide P-MOSFET's

A. Bravaix; D. Goguenheim; Dominique Vuillaume; V. Thirion; A. Straboni; M. Haond


device research conference | 2010

Analysis of S/D Engineering through Short Channel Effect and Hot Carrier Injection behavior in a 0.35μm CMOS Technology

E. Vandenbossche; Ph. Delpech; N. Revil; M. Haond


device research conference | 2010

Advanced Ti Salicide Process for Sub-0.2 μm CMOS

M-L. Rostoll; D. Maury; J.L. Regolini; M. Haond; Philippe Delpech; P. Gayet; M. LeContellec


device research conference | 2010

Shallow Trench Isolation for Sub 1/4 Micron CMOS Technologies

P. Sallagoity; M. Paoli; M. Haond


european solid state device research conference | 1994

Electron Trapping and Detrapping in 8 nm-Thick Gate-Oxide of p + Poly-Gate p-MOSFET's

A. Bravaix; Dominique Vuillaume; V. Thirion; Alain Straboni; M. Haond


european solid state device research conference | 1994

Integration of Innovative Process Modules in a Full 0.35 μm CMOS Process and Circuit Demonstration

M. Haond; M. Lerme


european solid state device research conference | 1993

Selective CVD TiSi 2 for Sub-0.5 μm N+/P+ CMOS Devices

M. Haond; J.L. Regolini

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A. Bravaix

Centre national de la recherche scientifique

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D. Goguenheim

Centre national de la recherche scientifique

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