E. Monteil

CHIPIX65: Developments on a new generation pixel readout ASIC in CMOS 65 nm for HEP experiments

Pixel detectors at HL-LHC experiments or other future experiments are facing new challenges, especially in terms of unprecedented levels of radiation and particle flux. This paper describes the progress made by the CHIPIX65 project of INFN for the development of a new generation readout ASIC using CMOS 65 nm technology.

A low-power low-noise synchronous pixel front-end chain in 65 nm CMOS technology with local fast ToT encoding and autozeroing for extreme rate and radiation at HL-LHC

A low-power and low-noise synchronous front-end chain in a commercial 65 nm CMOS technology suitable for the future pixel upgrades at the CERN Large Hadron Collider (LHC) is presented. A shaper-less Charge-Sensitive Amplifier (CSA) with constant current feedback provides triangular pulse shaping for linear Time-over-Threshold (ToT) charge measurement. The sensor leakage current is compensated by the same feedback network. A track-and-latch voltage comparator is adopted for the hit discrimination. The hit generation is synchronized with a 40 MHz clock, minimizing time-walk issues in the time-stamp assignment. Fast ToT charge encoding up to 8-bit resolution can be retrieved at the pixel level exploiting a high-frequency self-generated clock signal. This is obtained by turning the latch into a voltage-controlled oscillator (VCO) using asynchronous logic. Pixel-to-pixel threshold variations are compensated by means of an autozeroed scheme, thus avoiding the need of a on-pixel D/A converter. An array of 8 × 8 cells with 50 μm × 50 μm pixel size has been prototyped. Design specifications, implementation and test results are discussed.

RD53 Collaboration and CHIPIX65 Project for the development of an innovative Pixel Front End Chip for HL-LHC

Natale Demaria∗† INFN Sezione di Torino, Torino, Italy E-mail: demaria@to.infn.it F.Ciciriello, F.Corsi, C.Marzocca Politecnico di Bari, Bari, Italy G.De Robertis, F.Loddo, C.Tamma INFN Sezione di Bari, Bari, Italy V.Liberali, S.Shojaii, A.Stabile INFN Sezione di Milano and Universita degli Studi di Milano, Milano, Italy M.Bagatin, D.Bisello, S.Gerardin, S.Mattiazzo, L.Ding, P.Giubilato, A.Paccagnella INFN Sezione di Padova and Universita di Padova, Padova, Italy F.De Canio, L.Gaioni, M.Manghisoni, V.Re, G.Traversi, E.Riceputi INFN Sezione di Pavia and Universita di Bergamo, Bergamo, Italy L.Ratti, C.Vacchi INFN Sezione di Pavia and Universita di Pavia, Pavia, Italy R.Beccherle, G.Magazzu, F.Morsani, F.Palla INFN Sezione di Pisa, Pisa, Italy G.M.Bilei, M.Menichelli INFN Sezione di Perugia, Perugia, Italy E.Conti, S.Marconi, D.Passeri, P.Placidi INFN Sezione di Perugia and Department of Engineering, Universita di Perugia, Italy G.Dellacasa, G.Mazza, A.Rivetti, M.D.Da Rocha Rolo INFN Sezione di Torino, Torino, Italy E.Monteil, L.Pacher INFN Sezione di Torino and University of Torino, Torino, Italy

Pixel front-end with synchronous discriminator and fast charge measurement for the upgrades of HL-LHC experiments

The upgrade of the silicon pixel sensors for the HL-LHC experiments requires the development of new readout integrated circuits due to unprecedented radiation levels, very high hit rates and increased pixel granularity. The design of a very compact, low power, low threshold analog very front-end in CMOS 65 nm technology is described. It contains a synchronous comparator which uses an offset compensation technique based on storing the offset in output. The latch can be turned into a local oscillator using an asynchronous logic feedback loop to implement a fast time-over-threshold counting. This design has been submitted and the measurement results are presented.

Results from CHIPIX-FE0, a small-scale prototype of a new generation pixel readout ASIC in 65 nm CMOS for HL-LHC

CHIPIX65-FE0 is a readout ASIC in CMOS 65nm designed by the CHIPIX65 project for a pixel detector at the HL-LHC, consisting of a matrix of 64x64 pixels of dimension 50x50 μm2. It is fully functional, can work at low thresholds down to 250e− and satisfies all the specifications. Results confirm low-noise, fast performance of both the synchronous and asynchronous front-end in a complex digital chip. CHIPIX65-FE0 has been irradiated up to 600 Mrad and is only marginally affected on analog performance. Further irradiation to 1 Grad will be performed. Bump bonding to silicon sensors is now on going and detailed measurements will be presented. The HL-LHC accelerator will constitute a new frontier for particle physics after year 2024. One major experimental challenge resides in the inner tracking detectors, measuring particle position: here the dimension of the sensitive area (pixel) has to be scaled down with respect to LHC detectors. This paper describes the results obtained by CHIPIX65-FE0, a readout ASIC in CMOS 65nm designed by the CHIPIX65 project as small-scale demonstrator for a pixel detector at the HL-LHC. It consists of a matrix of 64x64 pixels of dimension 50x50 um2 pixels and contains several pieces that are included in RD53A, a large scale ASIC designed by the RD53 Collaboration: two out of three front-ends (a synchronous and an asynchronous architecture); several building blocks; a (4x4) pixel region digital architecture with central local buffer storage, complying with a 3 GHz/cm2 hit rate and a 1 MHz trigger rate maintaining a very high efficiency (above 99%). The chip is 100% functional, either running in triggered or trigger-less mode. All building-blocks (DAC, ADC, Band Gap, SER, sLVS-TX/RX) and very front ends are working as expected. Analog performance shows a remarkably low ENC of 90e-, a fast-rise time below 25ns and low-power consumption (about 4μA/pixel) in both synchronous and asynchronous front-ends; a very linear behavior of CSA and discriminator. No significant cross talk from digital electronics has been measured, achieving a low threshold of 250e-. Signal digitization is obtained with a 5b-Time over Threshold technique and is shown to be fairly linear, working well either at 80 MHz or with higher frequencies of 300 MHz obtained with a tunable local oscillator. Irradiation results up to 600 Mrad at low temperature (-20°C) show that the chip is still fully functional and analog performance is only marginally degraded. Further irradiation will be performed up to 1 Grad either at low or room temperature, to further understand the level of radiation hardness of CHIPIX65-FE0. We are now in the process of bump bonding CHIPIX65-FE0 to 3D and possibly planar silicon sensors during spring. Detailed results will be presented in the conference paper.

A prototype of a new generation readout ASIC in 65nm CMOS for pixel detectors at HL-LHC

The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started.