Alberto Stabile

Associative memory design for the fast track processor (FTK) at ATLAS

We propose a new generation of VLSI processors for pattern recognition, based on associative memory architecture, optimized for online track finding in high-energy physics experiments. We describe the architecture, the technology studies and the prototype design of a new associative memory project: it maximizes the pattern density on the ASIC, minimizes the power consumption and improves the functionality for the fast tracker processor proposed to upgrade the ATLAS trigger at LHC.

CHIPIX65: Developments on a new generation pixel readout ASIC in CMOS 65 nm for HEP experiments

Pixel detectors at HL-LHC experiments or other future experiments are facing new challenges, especially in terms of unprecedented levels of radiation and particle flux. This paper describes the progress made by the CHIPIX65 project of INFN for the development of a new generation readout ASIC using CMOS 65 nm technology.

A new XOR-based Content Addressable Memory architecture

In this paper we describe a Content Addressable Memory (CAM) architecture based on a new custom cell, called XORAM. The cell is composed by two main blocks: a 6T-SRAM, and a 4T-XOR logic gate. Each XORAM cell compares the input data on the bit line with the data stored in the 6T-SRAM cell. The output matching bit is obtained by performing a NOR operation between all bits of the XORAM cells storing the word. The proposed architecture is based on a fully-CMOS combinational logic, and it does nor require any precharge operation or control and timing logic. A compact full-custom layout has been designed for a memory organized in 18-bit words, to reduce both area and power consumption. Compared with a conventional selective precharge match-line technique, the proposed circuit occupies less area. Simulation results demonstrate that power consumption is reduced by a factor of 8.

Next generation associative memory devices for the FTK tracking processor of the ATLAS experiment

Higher LHC energy and luminosity increase the challenge of track reconstruction for the ATLAS trigger. To effectively handle the very high data rate, a dedicated hardware-based system has been designed. The Fast Track Trigger (FTK) will provide high quality track reconstruction over the entire detector volume to be run after the first level trigger has accepted an event. It will help to improve the efficiency and background rejection for triggers on tau leptons and b-hadrons by the second level trigger and help reduce the luminosity dependence of isolation requirements for electrons and muons. In this paper we present the status of associative memory design and its future development.

2D and 3D thin pixel technologies for the Layer0 of the SuperB Silicon Vertex Tracker

The high luminosity asymmetric e+e− collider SuperB, recently approved by the Italian Government, is designed to deliver a luminosity greater than 1036cm−2s−1 with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. An improved vertex resolution is required for precise time-dependent measurements and the SuperB Silicon Vertex Tracker will be equipped with an innermost layer of small radius (about 1.5 cm), resolution of 10 µm in both coordinates, low material budget (< 1% X0), and able to withstand a hit background rate of several tens of MHz/cm2. The ambitious goal of designing a thin pixel device matching these stringent requirements is being pursued with specific R&D programs on different technologies: CMOS MAPS, pixel sensors in vertical integration technology and hybrid pixels with small pitch and reduced material budget. The latest results on the characterization of the various pixel devices realized for the SuperB Layer0 will be presented.

Layout-oriented simulation of non-destructive single event effects in CMOS IC blocks

This paper presents a tool based on a two dimensional charge-collection simulation to study non-destructive single event effects in CMOS IC blocks. The interaction between the radiation particle and the p-n junctions is modeled at circuit level with a set of parasitic currents, which are injected into the nodes corresponding to the geometrical areas at or near the point where the particle hits the IC. A drift-diffusion model is used to obtain parasitic currents waveforms. By means of circuit simulations, single event transients and single event upsets can be obtained for different collision positions. From simulation results, a map can be drawn, showing the sensitivity to single events of different layout regions. By comparing sensitivity maps, the designer can choose the most robust layout with respect to single event effects. Layout design guidelines are proposed to improve radiation hardness.

RD53 Collaboration and CHIPIX65 Project for the development of an innovative Pixel Front End Chip for HL-LHC

Natale Demaria∗† INFN Sezione di Torino, Torino, Italy E-mail: demaria@to.infn.it F.Ciciriello, F.Corsi, C.Marzocca Politecnico di Bari, Bari, Italy G.De Robertis, F.Loddo, C.Tamma INFN Sezione di Bari, Bari, Italy V.Liberali, S.Shojaii, A.Stabile INFN Sezione di Milano and Universita degli Studi di Milano, Milano, Italy M.Bagatin, D.Bisello, S.Gerardin, S.Mattiazzo, L.Ding, P.Giubilato, A.Paccagnella INFN Sezione di Padova and Universita di Padova, Padova, Italy F.De Canio, L.Gaioni, M.Manghisoni, V.Re, G.Traversi, E.Riceputi INFN Sezione di Pavia and Universita di Bergamo, Bergamo, Italy L.Ratti, C.Vacchi INFN Sezione di Pavia and Universita di Pavia, Pavia, Italy R.Beccherle, G.Magazzu, F.Morsani, F.Palla INFN Sezione di Pisa, Pisa, Italy G.M.Bilei, M.Menichelli INFN Sezione di Perugia, Perugia, Italy E.Conti, S.Marconi, D.Passeri, P.Placidi INFN Sezione di Perugia and Department of Engineering, Universita di Perugia, Italy G.Dellacasa, G.Mazza, A.Rivetti, M.D.Da Rocha Rolo INFN Sezione di Torino, Torino, Italy E.Monteil, L.Pacher INFN Sezione di Torino and University of Torino, Torino, Italy

Characterisation of an Associative Memory Chip for high-energy physics experiments

This paper presents the approach used to characterize an Associative Memory Chip (AMChip) designed for the trigger systems of high-energy physics experiments in the Large Hadron Collider (LHC) at CERN. Pattern recognition is performed with Associative Memories (AM). A dedicated integrated circuit has been designed, fabricated and tested to verify that the proposed solution meets area, speed and current consumption requirements.

The Associative Memory Serial Link Processor for the Fast TracKer (FTK) at ATLAS

The Fast TracKer (FTK) is an extremely powerful and very compact processing unit, essential for efficient Level 2 trigger selection in future high-energy physics experiments at the LHC. FTK employs Associative Memories (AM) to perform pattern recognition; input and output data are transmitted over serial links at 2 Gbit/s to reduce routing congestion at the board level. Prototypes of the AM chip and of the AM board have been manufactured and tested, in preparation of the imminent design of the final version.

Performance of the AMBFTK board for the FastTracker processor for the ATLAS detector upgrade

Modern experiments at hadron colliders search for extremely rare processes hidden in a very large background. As the experiment complexity and the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. The FastTracker (FTK) processor for the ATLAS experiment offers extremely powerful, very compact and low power consumption processing units for the future, which is essential for increased efficiency and purity in the Level 2 trigger selection through the intensive use of tracking. Pattern recognition is performed with Associative Memories (AM). The AMBFTK board and the AMchip04 integrated circuit have been designed specifically for this purpose. We report on the preliminary test results of the first prototypes of the AMBFTK board and of the AMchip04.