E. Sano

An 80-Gb/s optoelectronic delayed flip-flop IC using resonant tunneling diodes and uni-traveling-carrier photodiode

This paper describes an 80-Gb/s optoelectronic delayed flip-flop (D-FF) IC that uses resonant tunneling diodes (RTDs) and a uni-traveling-carrier photodiode (UTC-PD). A circuit design that considers the AC currents passing through RTDs and UTC-PD is key to boosting circuit operation speed. A monolithically fabricated IC operated at 80 Gb/s with a low power dissipation of 7.68 mW. The operation speed of 80 Gb/s is the highest among all reported flip-flops. To clarify the maximum operation speed, we analyze the factors limiting circuit speed. Although the bandwidth of UTC-PD limits the maximum speed of operation to 80 Gb/s at present, the circuit has the potential to offer 100-Gb/s-class operation.

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector

We present a 40-Gbit/s-class clock and data recovery (CDR) circuit with a new lock detector. The lock detector operates robustly with a linear-type phase detector. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40, 43, and 45-Gbit/s PRBS with a length of 2/sup 31/-1. By attaching a frequency search and phase control (FSPC) circuit to the chip, the CDR circuit pulls in throughout a 39-45 Gbit/s range. The fabricated IC dissipates 1.89 W at a supply voltage of -4.5V.

An inverted microstrip line IC structure for ultra high-speed applications

An inverted microstrip line IC structure for ultra high-speed applications is proposed. It allows a a very low-parasitic-impedance module with a flip-chip bonding, a small IC size, and performance improvements for high-speed digital ICs.<<ETX>>

A 40-Gbit/s optical repeater circuits using InAlAs/InGaAs HEMT digital IC chip set

This paper describes an InAlAs/InGaAs HEMT digital IC chip set which includes a multiplexer, demultiplexer, decision circuit, and frequency divider. Electrically multiplexed and demultiplexed 40-Gbit/s transmission is successfully performed.

Design and performance of clock recovery GaAs ICs for high-speed optical communication systems

Design and performance of clock-recovery GaAs ICs are presented. Four kinds of ICs were developed: a limiting amplifier, a tuning amplifier, a rectifier, and a differentiator. The cascaded limiting amplifier together with a tuning amplifier achieved a 58-dB gain and a 10-degree phase deviation with 20-dB input dynamic range at 10 GHz. A clock-recovery circuit successfully extracts a low-jitter 10-GHz clock signal of 1-dBm constant power from 10-Gb/s NRZ pseudorandom bit streams using a pulse pattern generator. >

A fully integrated 40-Gbit/s clock and data recovery circuit using InP/InGaAs HBTs

An integrated clock and data recovery (CDR) circuit is a key element for optical communication systems at 40 Gbit/s. We present a fully integrated 40-Gbit CDR circuit fabricated using InP/InGaAs HBTs. The circuit contains a linear-type phase detector and a full-data-rate voltage-controlled oscillator. Error-free operation and wide eye opening were obtained for 40-Gbit/s pseudorandom bit sequence (PRBS) with a length of 2/sup 23/-1. The fabricated IC dissipates 1.71 W at a supply voltage of -4.5 V.

4-bit multiplexer/demultiplexer chip set for 40-Gbit/s optical communication systems

We have designed and fabricated a low-power 4:1 multiplexer (MUX), 1:4 demultiplexer (DEMUX) and full-clock-rate 1:4 DEMUX with a clock and data recovery (CDR) circuit using undoped-emitter InP-InGaAs HBTs. Our HBTs exhibit an f/sub T/ of approximately 150 GHz and an f/sub max/ of approximately 200 GHz at a collector current density of 50 kA/spl mu/m/sup 2/. In the circuit design, we utilize emitter-coupled logic and current-mode logic series gate flip-flops and optimized the collector current density of each transistor to achieve low-power operation at required high bit rates. Error-free operation at bit rates of up to 50 Gbit/s were confirmed for the 4:1 MUX and 1:4 DEMUX, which dissipates 2.3 and 2.5 W, respectively. In addition, the full-clock-rate 1:4 DEMUX with the CDR achieved 40-Gbit/s error-free operation.

A 40-Gbit/s monolithic digital OEIC module composed of uni-traveling-carrier photodiode and InP HEMT decision circuit

The authors describe an optoelectronic decision IC that is a monolithic combination of a uni-traveling-carrier photodiode and 0.1 /spl mu/m InAlAs-InGaAs-InP HEMTs for broadband optical fiber communication systems. The fabricated chip is packaged as an OEIC module, and 40 Gbit/s error-free operation is confirmed for an RZ data stream at the clock rate of 40 GHz for the first time.

A novel terahertz plasma-wave photomixer with resonant-cavity enhanced structure

Two-dimensional (2D) plasmon in a submicron transistor channel can make resonant oscillation in the terahertz range. We propose a novel terahertz plasma-wave photomixer that can improve the conversion gain and terahertz radiation power. The photomixer is based on a high-electron mobility transistor (HEMT) and incorporates doubly interdigitated grating strips for the gate electrodes that periodically localize the 2D plasmons in sub 100-nm regions with a micron-order interval. A vertical cavity structure is formed in between the top metal grating and a terahertz mirror placed at the backside. FDTD simulation demonstrates that a newly-introduced vertical cavity structure effectively enhances the conversion gain and radiation power.

Over-40-Gb/s IC module technology using 8-mm-square leadless chip carrier packages mounted on four-layer resin printed circuit boards

A key technology for realizing small, low-cost IC modules for over-40-Gb/s optical communication systems has been developed. The technology mainly features 8-mm-square leadless chip carrier (LCC) packages and four-layer resin printed circuit boards (PCBs). It was applied to build a prototype multichip 1:4 DEMUX module operating at 45 Gb/s.