T. Enoki

High-performance 0.1-/spl mu/m gate enhancement-mode InAlAs/InGaAs HEMT's using two-step recessed gate technology

Novel approach for making high-performance enhancement-mode InAlAs/InGaAs HEMTs (E-HEMTs) is described for the first time. Most important issue for the fabrication of E-HEMTs is the suppression of the parasitic resistance due to side-etching around the gate periphery during gate recess etching. Two-step recessed gate technology is utilized for this purpose. The first step of the gate recess etching removes cap layers wet-chemically down to an InP recess-stopping layer and the second step removes only the recess-stopping layer by Ar plasma etching. The parasitic component for source resistance is successfully reduced to less than 0.35 /spl Omega//spl middot/mm. Etching selectivities for both steps are sufficient not to degrade uniformity of devices on the wafer. The resulting structure achieves a positive threshold voltage of 49.0 mV with high transconductance. Due to the etching selectivity, the standard deviation of the threshold voltage is as small as 13.3 mV on a 3-in wafer. A cutoff frequency of 208 GHz is obtained for the 0.1-/spl mu/m gate E-HEMTs. This is therefore one of the promising devices for ultra-high-speed applications.

0.3- mu m advanced SAINT FET's having asymmetric n/sup +/-layers for ultra-high-frequency GaAs MMIC's

Improvements in the microwave performance and noise performance of buried p-layer self-aligned gate (BP-SAINT) FETs are discussed. Specifically, a self-aligned gate electrode and an asymmetric n/sup +/-layer structure are investigated. The self-aligned gate electrode reduces parasitic gate capacitances by 0.13 to 0.23 pF/mm compared with a conventional BP-SAINT FET. The asymmetric n/sup +/-layer structure reduces short-channel effects (drain conductance, threshold voltage shift, etc.) and gate-drain capacitance. A 0.3- mu m gate-length FET was realized without an increase of short-channel effects by using an asymmetric n/sup +/-layer structure (advanced SAINT). Improvement of microwave performance is confirmed in this FET structure. >

A high-Q broad-band active inductor and its application to a low-loss analog phase shifter

The proposed high-Q broad-band active inductor utilizes frequency-insensitive negative resistance to compensate constant internal losses caused by the drain-to-source conductance of the field-effect transistors (FETs), the dc bias circuit, and several other factors. The measured frequency range of the fabricated InAlAs/InGaAs/InP HEMT active inductor is 6 to 20 GHz for Q values greater than 100, and 7 to 15 GHz for Q values greater than 1000. A low-loss analog phase shifter is also fabricated at C-band. This is constructed with the active inductors, the varactor diodes and the low-loss multilayer broad-side coupler in a MIC structure. Since the constant negative resistance of the active inductors also compensates the line loss of the coupler and the varactor diodes series resistance, the measured results show a good insertion loss performance with a large phase shift. A phase shift of more than 225/spl deg/ within a 0.8 dB insertion loss from 4.7 to 6.7 GHz, another of more than 180/spl deg/ within 1.3 dB insertion loss from 3.7 to 8.5 GHz, and one more of more than 90/spl deg/ within 1.4 dB insertion loss from 3.5 to 10.6 GHz were obtained.

120-GHz Tx/Rx chipset for 10-Gbit/s wireless applications using 0.1 /spl mu/m-gate InP HEMTs

This paper describes the development of a InP-HEMT MMIC chipset for 120-GHz wireless applications. The transmitter chip includes a frequency doubler for carriers, an ASK modulator, an RF band-pass filter, and a power amplifier. The receiver chip includes a low-noise amplifier and an ASK demodulator. A back-to-back test of the chipset has shown it to be fully functional at 10-Gbit/s data rate with BER=e-12 at -45.7-dBm input power of the receiver chip. To our knowledge, this is the first report of the development of highly integrated MMIC chipset operating at 120 GHz for wireless data communication.

100-Gb/s multiplexing and demultiplexing IC operations in InP HEMT technology

This paper describes the 100-Gb/s multiplexing operation of a selector IC and demultiplexing operation of a D-type flip-flop (D-FF) using production-level 0.1-/spl mu/m-gate-length InP HEMT IC technology. To boost the operating speed of the selector IC, a selector core circuit directly drives an external 50-/spl Omega/ load, and is included in the output stage. In addition, a test chip containing the selector and a D-FF to confirm error-free operation of these circuits was designed. The fabricated selector IC exhibited clear eye openings at 100 Gb/s, and its error-free operation was confirmed by using the test chip.

A 120-GHz millimeter-wave MMIC chipset for future broadband wireless access applications

A flexible CPW-MMIC (coplaner-waveguide monolithic microwave integrated circuit) chipset has been fabricated for 120 GHz future broadband wireless systems. The power amplifier has small signal gain of 8.5 dB from 115 to 135 GHz. The 1 dB compression point is 3 dBm at 120 GHz. We employed a traveling wave switch configuration for the ASK modulator. The insertion loss of the switch is less than 1.5 dB and the on-off ratio is more than 13.5 dB at 120 GHz. For the ASK modulator-demodulator chipset, the measured BER is 1e/sup -10/ for 10 Gbit/s PRBS 2/sup 11/-1 data at -13 dBm input power and 120 GHz RF frequency. The frequency doubler has an output power of -11 dBm at 120 GHz with fundamental and harmonics rejection better than 30 dBc.

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector

We present a 40-Gbit/s-class clock and data recovery (CDR) circuit with a new lock detector. The lock detector operates robustly with a linear-type phase detector. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40, 43, and 45-Gbit/s PRBS with a length of 2/sup 31/-1. By attaching a frequency search and phase control (FSPC) circuit to the chip, the CDR circuit pulls in throughout a 39-45 Gbit/s range. The fabricated IC dissipates 1.89 W at a supply voltage of -4.5V.

A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator

A clock and data recovery (CDR) circuit with a novel two-mode phase comparator is proposed. The 10-Gb/s CDR integrated circuit (IC) operates both for consecutive identical digits (CID) and data transition density variations. This advance is achieved through the use of our novel two-mode phase comparator, which enables us to determine an optimal phase-locked loop parameter for various data patterns. Experimental results show that the jitter generation of the CDR IC is less than 7 pspp for a 2/sup 7/-1 pseudorandom bit sequence with up to 1024 CIDs. The results also show that the jitter transfer and jitter tolerance are unaffected by data transition density factors of between 1/8 and 1/2.

50-Gbit/s 4-bit multiplexer/demultiplexer chip-set using InP HEMTs

This paper reports on the 50-Gbit/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DMUX) chip-set using InP HEMTs. In order to achieve high and wide-range bit-rate operation, timing design inside the ICs was precisely executed. The packaged MUX and DMUX achieved 50 Gbit/s back-to-back error-free operation for 2/sup 31/-1 pseudo-random bit streams (PRBS). Furthermore, the MUX operated from 4 to 50 Gbit/s with >1 V/sub pp/ output amplitude, and the DMUX exhibited >180-degrees phase margin from 4 to 50 Gbit/s for 2/sup 31/-1 PRBS.

Analysis of transient response and operating speed of MOBILE

To clarify the relationship between the figures-of-merit of resonant tunneling diodes and the operating speed of a monostable-bistable transition logic element (MOBILE), we investigated the transient response of a MOBILE using a simple current-voltage characteristics model. We found that an unstable point in a MOBILE affects its operation, and false operation occurs when the amplitude of the clock signal is inappropriate. From a calculation of transient time using peak-to-valley current ratio (PVR) and peak current density (j/sub P/) as parameters, we also discovered that a sufficiently high j/sub P/ and higher PVR (>6) are necessary for high-speed operations.