Kimikazu Sano

100-Gb/s multiplexing and demultiplexing IC operations in InP HEMT technology

This paper describes the 100-Gb/s multiplexing operation of a selector IC and demultiplexing operation of a D-type flip-flop (D-FF) using production-level 0.1-/spl mu/m-gate-length InP HEMT IC technology. To boost the operating speed of the selector IC, a selector core circuit directly drives an external 50-/spl Omega/ load, and is included in the output stage. In addition, a test chip containing the selector and a D-FF to confirm error-free operation of these circuits was designed. The fabricated selector IC exhibited clear eye openings at 100 Gb/s, and its error-free operation was confirmed by using the test chip.

An 80-Gb/s optoelectronic delayed flip-flop IC using resonant tunneling diodes and uni-traveling-carrier photodiode

This paper describes an 80-Gb/s optoelectronic delayed flip-flop (D-FF) IC that uses resonant tunneling diodes (RTDs) and a uni-traveling-carrier photodiode (UTC-PD). A circuit design that considers the AC currents passing through RTDs and UTC-PD is key to boosting circuit operation speed. A monolithically fabricated IC operated at 80 Gb/s with a low power dissipation of 7.68 mW. The operation speed of 80 Gb/s is the highest among all reported flip-flops. To clarify the maximum operation speed, we analyze the factors limiting circuit speed. Although the bandwidth of UTC-PD limits the maximum speed of operation to 80 Gb/s at present, the circuit has the potential to offer 100-Gb/s-class operation.

Silica-based, compact and variable-optical-attenuator integrated coherent receiver with stable optoelectronic coupling system

We demonstrate a compact and variable-optical-attenuator (VOA) integrated coherent receiver with a silica-based planar lightwave circuit (PLC). To realize the compact receiver, we integrate a VOA in a single PLC chip with polarization beam splitters and optical 90-degree hybrids, and employ a stable optoelectronic coupling system consisting of micro lens arrays and photodiode (PD) subcarriers with high-speed right-angled signal lines. We integrate a VOA and a coherent receiver in a 27x40x6 mm package, and successfully demodulate a 128-Gbit/s polarization division multiplexed (PDM) quadrature phase shift keying (QPSK) signal with a VOA-assisted wide dynamic range of more than 30 dB.

A 20-Gs/s Track-and-Hold Amplifier in InP HBT Technology

This paper presents a 20-Gs/s track-and-hold amplifier (THA) fabricated InP HBT technology. This THA is capable of operating under relatively high input voltages. The THA uses a fully differential architecture with a switched emitter-follower. To mitigate the pedestal error due to the feedthrough attenuation network, we added degeneration resistors in the feedthrough attenuation block. Measured total harmonic distortion is below -40 dB at low input frequencies, and -18 dB at frequency of 9.9 GHz.

Ultrahigh-Speed Low-Power DACs Using InP HBTs for Beyond-100-Gb/s/ch Optical Transmission Systems

This paper presents the circuit designs and measured performance of two ultrahigh-speed low-power 6-b digital-to-analog converters (DACs) using InP-based heterojunction bipolar transistors (HBTs) for beyond-100-Gb/s/ch optical transmission systems. The first design is based on an R-2R ladder-based current-steering architecture with a novel double-sampling technique that relaxes the speed restraints for the DAC and helps achieve ultrahigh-speed operation. The DAC with the double-sampling technique achieves an excellent sampling speed of up to 32 GS/s with low power consumption of 1.4 W. The second design is based on a new timing alignment technique. The DAC with the timing alignment technique operates at a sampling rate of 28 GS/s with very low power consumption of 0.95 W and achieves an excellent figure of merit (0.53 pJ per conversion step). It provides a clear multilevel modulated signal for QAM transmission and can be applied to beyond-100-Gb/s/ch optical transmission systems.

50-Gbit/s 4-bit multiplexer/demultiplexer chip-set using InP HEMTs

This paper reports on the 50-Gbit/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DMUX) chip-set using InP HEMTs. In order to achieve high and wide-range bit-rate operation, timing design inside the ICs was precisely executed. The packaged MUX and DMUX achieved 50 Gbit/s back-to-back error-free operation for 2/sup 31/-1 pseudo-random bit streams (PRBS). Furthermore, the MUX operated from 4 to 50 Gbit/s with >1 V/sub pp/ output amplitude, and the DMUX exhibited >180-degrees phase margin from 4 to 50 Gbit/s for 2/sup 31/-1 PRBS.

Photoreceiver module using an InP HEMT transimpedance amplifier for over 40 gb/s

We developed a photoreceiver module for over 40 Gb/s that uses two ultrahigh- speed device technologies: an InP HEMT transimpedance amplifier (TIA) and a uni-traveling-carrier photodiode (UTC-PD). The TIA was designed to have a wide dynamic range by using cascade HEMT topology for the output buffer. We found that reducing the standing wave at the PD-TIA interface by decreasing the change of arg(S/sub 11/) of the TIA within the required frequency region is important for increasing the bandwidth of the module. We obtained a minimum sensitivity of -7.6 dBm and a dynamic range of 11 dB for 43-Gb/s nonreturn-to-zero optical input signal. Error-free operation of the module was confirmed at a data rate of 50 Gb/s.

A 60-GS/s 6-Bit DAC in 0.5-im InP HBT Technology for Optical Communications Systems

This paper presents a 60-GS/s 6-bit digital-to-analog converter (DAC) for beyond-100-Gb/s/ch optical communications systems. The DAC was designed and fabricated using our in-house 0.5-im InP HBT technology, which yields a peak ft of 290 GHz, a peak fmax of 320 GHz, and a BVCEO of approximately 4 V. We used a simple R-2R ladder-based current-steering architecture to achieve both high-speed and low-power operation, and a timing alignment technique to suppress glitch noise and improve dynamic linearity. The DAC can provide clear multilevel signals for quadrature amplitude modulation (QAM) transmission at a sampling rate of up to 60 GS/s (60 Gbaud). To our knowledge, our DAC offers the highest sampling rate of any previously reported DAC, and it can be applied to 400-Gb/s/ch-class optical communications systems.

50-gbit/s InP HEMT 4 : 1 multiplexer/1 : 4 demultiplexer chip set with a multiphase clock architecture

A 50-Gbit/s InP high electron-mobility transistor (HEMT) chip set of 4 : 1 multiplexer (MUX) and 1 : 4 demultiplexer (DMUX) integrated circuits (ICs) with a multiphase clock (MPC) architecture is described. The MPC architecture employs a quarter-rate four-phase clock generated by a toggle flip-flop inside the ICs, which reduces the number of circuit elements and lowers the power consumption. The fabricated 4 : 1 MUX and 1 : 4 DMUX ICs exhibited 50-Gbit/s error-free operations for 2/sup 31/-1 pseudorandom bit sequences with 1.71- and 1.42-W power consumption, respectively. Compared to conventional tree-type 4 : 1 MUX and 1 : 4 DMUX ICs using InP HEMTs, the MPC 4 : 1 MUX and 1 : 4 DMUX ICs operate at the same operating speed with less than one-third power consumption.

In-band OSNR monitor with high-speed integrated Stokes polarimeter for polarization division multiplexed signal.

An in-band optical signal-to-noise ratio (OSNR) monitor is proposed, based on an instantaneous polarization state distribution analysis. The proposed monitor is simple, and is applicable to polarization division multiplexed signals. We fabricate a high-speed Stokes polarimeter that integrates a planar lightwave circuit (PLC) based polarization filter, high-speed InP/InGaAs photodiodes and InP hetero-junction bipolar transistor (HBT) trans-impedance amplifiers (TIA). We carry out proof-of-concept experiments with the fabricated polarimeter, and successfully measure the OSNR dependent polarization distribution with 100-Gb/s dual polarization quadrature phase shift keying (DP-QPSK) signals.