E. Vrancken

Record I ON /I OFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability

We report on a 65 nm Ge pFET with a record performance of Ion = 478muA/mum and Ioff,s= 37nA/mum @Vdd= -1V. These improvements are quantified and understood with respect to halo/extension implants, minimizing series resistance and gate stack engineering. A better control of Ge in-diffusion using a low-temperature epi-silicon passivation process allows achieving 1nm EOT Ge-pFET with increased performance.

High FET Performance for a Future CMOS

In Germanium-based metal-oxide-semiconductor field-effect transistors, a high-quality interfacial layer prior to high-¿ deposition is required to achieve low interface state densities and prevent Fermi level pinning. In this letter, the physical and electrical properties of a Ge/GeO2/Al2O3 gate stack are investigated. The GeO2 interlayer grown by radical oxidation and the formation of a germanate (GeAlOX) layer at the interface provide a stable high-quality passivation of the Ge channel. High carrier mobilities (235 cm2/V·s for electrons and 265 cm2/V·s for holes) are demonstrated for a relatively low 3.7-nm equivalent oxide thickness (EOT), enabling the realization of a high-performance CMOS technology with potential EOT scaling.

\hbox{GeO}_{2}

Biaxially-strained Ge p-channel field effect transistors (pFETs) have been fabricated for the first time in a 65 nm technology. The devices are designed to have a reduced effective oxide thickness (EOT) while maintaining minimized short channel effects. Low and high field transport has been studied by in-depth electrical characterization, showing a high hole-mobility that is enhanced by up to 70% in the strained devices. The important role of pocket implants in degrading the drive current is highlighted. Using a judicious implantation scheme, we demonstrate a significant gain in on-current (up to 35%) for nanoscaled strained Ge pFETs. Simultaneous optimization of the gate metal and dielectric, together with the corresponding uniaxial stress engineering, is identified as a promising path for further performance enhancement.

-Based Technology

1. Abstract: For the first time, high hole-mobility 65nm biaxially-strained Ge-pFETs, with reduced EOT while maintaining minimized SCE, have been fabricated and electrically characterized in-depth for the low and high field transport. The important role of pocket implants in drive current degradation is highlighted. Using a judicious implantation scheme, we demonstrate a significant ION gain (up to 35%) for nanoscaled strained Ge pFETs. Simultaneous optimization of metal gate and dielectric, together with the corresponding unixial stress engineering, is clearly the most promising path for further performance enhancement.