G. Winderickx

High Q inductor add-on module in thick Cu/SiLK/sup TM/ single damascene

Thick Cu single damascene inductors with very high Q factors are integrated on top of a standard aluminum 3LM BEOL process. Obtained Q factors are more than four times higher than Q factors of the inductors of the same geometry processed in the Al 3LM BEOL. For an inductor of 2.8 nH inductance, a Q peak of 24 at 2 GHz was reached by using 4 /spl mu/m thick Cu on a 2 /spl mu/m IMD oxide layer.

High performance Ge pMOS devices using a Si-compatible process flow

Ge pMOS mobilities up to 358 cm²/Vs are demonstrated using a Si-compatible process flow without the incorporation of strain. EOT is approximately 12 Aring with a gate leakage less than 0.01 A/cm ² at V_t+ 0.6 V. Ge transistors are characterized with gate lengths ranging from 10 mum down to 0.125 mum, the shortest ever reported. We also present the best Ge pMOS drain current to date of 790 muA/mum at V_gt = V_d = -1.5V for an L_g of 0.19 mum

Record I ON /I OFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability

We report on a 65 nm Ge pFET with a record performance of Ion = 478muA/mum and Ioff,s= 37nA/mum @Vdd= -1V. These improvements are quantified and understood with respect to halo/extension implants, minimizing series resistance and gate stack engineering. A better control of Ge in-diffusion using a low-temperature epi-silicon passivation process allows achieving 1nm EOT Ge-pFET with increased performance.

Observation and Suppression of Nickel Germanide Overgrowth on Germanium Substrates with Patterned SiO2 Structures

We have investigated the reactions of thin Ni films on Ge-on-Si substrates with patterned SiO 2 structures. For rapid thermal anneals (RTAs) hotter than ∼300°C, an undesirable growth mode is observed whereby voids form in the Ge next to the SiO 2 and germanide grows over the SiO 2 . A model is proposed in which Ge is the dominant diffusing species during germanidation in the presence of topographies with Ge/SiO 2 boundaries. This undesirable growth is suppressed by the use of a 2-RTA process, preferably involving an RTA1 at ∼250°C, followed by a selective etch of the unreacted Ni, and an RTA2 at ∼330°C.

Investigation of PECVD dielectrics for nondispersive metal-insulator-metal capacitors

Metal-insulator-metal (MIM) capacitors with PECVD nitride exhibit trap-induced dispersive behavior, which leads to degradation in capacitor linearity at low frequencies, limiting the accuracy in precision analog circuits. While LPCVD oxide results in nondispersive behavior, the high deposition temperature excludes the use of LPCVD dielectrics for MIM capacitors using the standard back-end metal layers as capacitor bottom plates. The latter is preferred in view of the low substrate coupling needed for RF applications. In this work, alternative PECVD dielectrics have been investigated with respect to frequency dependence of voltage linearity, hysteresis, matching, and leakage characteristics. It will be shown that ONO stacks offer a combination of good voltage linearity, absence of dispersive behavior and hysteresis, excellent matching, and low leakage.

Heavy ion implantation in Ge: Dramatic radiation induced morphology in Ge

High dose ion implantation of heavy elements in Ge induces a rough surface and profile distortions when measured with secondary ion mass spectrometry. In the case of Sb large subsurface holes are also induced by the implantation. The formation of these subsurface structures starts abruptly at a dose between 5∙1014 and 1015at∕cm2. The addition of a SiO2 capping layer on top of Ge prevents the formation of the surface roughness, but has limited impact on the void formation. These voids originate from vacancy clustering during the implant process. Anneal studies show that it is impossible to remove these structures by annealing, limiting the usefulness of high dose Sb implants in Ge for junction formation. In the case of As implantation a similar surface roughness is seen but no void formation. Adding a cap layer removes the surface roughness in this case and improves the secondary ion mass spectroscopy profiles.

A 400GHz f MAX fully self-aligned SiGe:C HBT architecture

An improved fully self-aligned SiGe:C HBT architecture featuring a single-step epitaxial collector-base process is described. An fMAX value of 400GHz is reached by structural as well as intrinsic advancements made to the HBT device.

High Hole Mobility in 65 nm Strained Ge p-Channel Field Effect Transistors with HfO2 Gate Dielectric

Biaxially-strained Ge p-channel field effect transistors (pFETs) have been fabricated for the first time in a 65 nm technology. The devices are designed to have a reduced effective oxide thickness (EOT) while maintaining minimized short channel effects. Low and high field transport has been studied by in-depth electrical characterization, showing a high hole-mobility that is enhanced by up to 70% in the strained devices. The important role of pocket implants in degrading the drive current is highlighted. Using a judicious implantation scheme, we demonstrate a significant gain in on-current (up to 35%) for nanoscaled strained Ge pFETs. Simultaneous optimization of the gate metal and dielectric, together with the corresponding uniaxial stress engineering, is identified as a promising path for further performance enhancement.

Ge deep sub-micron pFETs with etched TaN metal gate on a high-k dielectric, fabricated in a 200mm silicon prototyping line

We report for the first time on deep sub-micron Ge pFETs with physical gate lengths down to 0.151 /spl mu/m. The devices are made using a silicon-like process flow, with a directly etched gate stack consisting of TaN gate on an ALD or MOCVD HfO/sub 2/ dielectric. Promising drive currents are found. Various issues such as the severe short channel effects (SCE), the increased diode leakage compared to Si and the high amount of interface states (N/sub it/) are addressed. The need for an alternative Ge substrate pre-treatment and subsequent high-k gate dielectric deposition to push EOT values below 1 nm is illustrated.

High Hole-Mobility 65nm Biaxially-Strained Ge-pFETs: Fabrication, Analysis and Optimization

1. Abstract: For the first time, high hole-mobility 65nm biaxially-strained Ge-pFETs, with reduced EOT while maintaining minimized SCE, have been fabricated and electrically characterized in-depth for the low and high field transport. The important role of pocket implants in drive current degradation is highlighted. Using a judicious implantation scheme, we demonstrate a significant ION gain (up to 35%) for nanoscaled strained Ge pFETs. Simultaneous optimization of metal gate and dielectric, together with the corresponding unixial stress engineering, is clearly the most promising path for further performance enhancement.