Joshua Tseng

Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization

A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO₂ based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and T_inv values of ˜5 Å and ˜8 Å respectively for both n and pMOS devices. The drive currents at I_off=100 nA/μm with V_DD=1 V is 1.4 mA/μm and 0.6 mA/μm (no SiGe source/drain) for n and pMOS respectively. The technology further offers low n/pMOS V_T of 0.3/-0.4V, good V_T-uniformity, and V_T-matching and very high cutoff frequencies at ˜290-340 GHz for 38 nm nMOS devices. A replacement poly gate process is used to further improve upon the pMOS effective work function. TDDB lifetimes over 10 years are reported while BTI indicates potential reliability challenges.

8Å T inv gate-first dual channel technology achieving low-V t high performance CMOS

We report low V<inf>t</inf> (V<inf>t,Lg=1µm</inf>=±0.26V) high performance CMOS devices with ultra-scaled T<inf>inv</inf> down to T<inf>inv</inf>∼8Å using a gate-first dual Si/SiGe channel low-complexity integration approach. Compared to a dual dielectric cap gate-first integration scheme, the devices fabricated with the novel scheme show for the same high-k/metal gate stack (1) 3Å reduction in nMOS and pMOS T<inf>inv</inf> (2) 220mV lower long channel pMOS V<inf>t</inf> (3) 21%/12% pMOS/nMOS drive current increase at I<inf>off</inf>=100nA/µm and (4) 50% improvement in long channel pMOS Vt variability. For a fixed T<inf>inv</inf> of 12Å, a 4 times higher hole mobility and 350mV increase in NBTI 10years lifetime operating voltage are obtained.

Positive and negative bias temperature instability on sub-nanometer eot high-K MOSFETs

For the first time, positive and negative bias temperature instability (P/NBTI) mechanisms in sub-nanometer EOT devices are investigated in this study. It is shown that PBTI degradation in sub-nanometer EOT devices occurs by interface degradation, additionally to the oxide bulk trap filling which is the dominant mechanism in over 1 nm EOT devices. For NBTI, interface degradation remains as the main mechanism in sub-nano EOT devices, and additional high contribution of the high-k bulk defects can increase the degradation below 6A EOT.

High Hole Mobility in 65 nm Strained Ge p-Channel Field Effect Transistors with HfO2 Gate Dielectric

Biaxially-strained Ge p-channel field effect transistors (pFETs) have been fabricated for the first time in a 65 nm technology. The devices are designed to have a reduced effective oxide thickness (EOT) while maintaining minimized short channel effects. Low and high field transport has been studied by in-depth electrical characterization, showing a high hole-mobility that is enhanced by up to 70% in the strained devices. The important role of pocket implants in degrading the drive current is highlighted. Using a judicious implantation scheme, we demonstrate a significant gain in on-current (up to 35%) for nanoscaled strained Ge pFETs. Simultaneous optimization of the gate metal and dielectric, together with the corresponding uniaxial stress engineering, is identified as a promising path for further performance enhancement.

High Hole-Mobility 65nm Biaxially-Strained Ge-pFETs: Fabrication, Analysis and Optimization

1. Abstract: For the first time, high hole-mobility 65nm biaxially-strained Ge-pFETs, with reduced EOT while maintaining minimized SCE, have been fabricated and electrically characterized in-depth for the low and high field transport. The important role of pocket implants in drive current degradation is highlighted. Using a judicious implantation scheme, we demonstrate a significant ION gain (up to 35%) for nanoscaled strained Ge pFETs. Simultaneous optimization of metal gate and dielectric, together with the corresponding unixial stress engineering, is clearly the most promising path for further performance enhancement.

Key sub 1nm EOT CMOS enabler by comprehensive PMOS design

A high performance CMOS HK/MG sub 1nm EOT solution is demonstrated. The drive currents at Ioff = 100 nA/μm with VDD = 1 V are 1.25 mA/μm and 0.56 mA/μm for n and pMOS respectively without strain boost. Through a novel process integration design, PMOS EWF roll-off and NBTI problems with EOT scaling are overcome until sub 1nm EOT region. The PMOS -0.25V Vt @1um Lg and NBTI 10 years life time @0.7V overdrive are thus offered with 0.94nm EOT. Mechanisms and guidelines for solving theses issues are provided after a comprehensive study here. These concepts are beneficial to either gate-first or gate-last approach with EOT scaling.