Eden Zielinski

Overview Of Process Integration Issues For Low K Dielectrics

The era of silicon Ultra-Large-Scale-Integration (ULSI) has spurred an everincreasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. Both interconnect resistance and capacitance play key roles in overall performance, but modeling simulations have highlighted the importance of reducing parasitic capacitance to manage crosstalk, power dissipation and RC delay. New dielectric materials with lower permittivity (k) are needed to meet this challenge. This paper summarizes the process integration and reliability issues associated with the use of novel low k materials in multilevel interconnects.

Inorganic antireflective coating process for deep-UV lithography

Antireflective coatings (ARCs) have been used to enhance IC lithography for years, however, many conventional bottom ARCs can no longer maintain acceptable linewidth control, cannot meet stringent deep-UV (DUV) photoresist processing requirements, and increase the etch complexity. In this paper, we report the development of an inorganic ARC for DUV lithography in sub-0.25 micrometer advanced device applications. Plasma-enhanced chemical vapor deposition (PECVD) is employed to deposit a dielectric film silicon oxynitride (SixOyNz) with specific optical properties. The three optical parameters of the SixOyNz film: refractive index n, extinction coefficient k, and thickness d are specifically designed to ensure that the reflection light that passes through the ARC/substrate is equal in amplitude and opposite in phase to the reflected light from the resist/ARC interface. The reflection light is canceled by destructive interference and therefore photoresist receives the minimum substrate reflection wave. Using this technique, we have successfully patterned features at 0.25 micrometer and below. The dielectric film can not only function as an ARC layer, but also serve as a hardmask for the pattern transfer etch process. With an aggressive etch bias process, linewidths down to 0.60 micrometer poly-Si gate are achieved with good linewidth control (3(sigma) less than 12 nm) and a near perfect linearity. For the marginal metal etch resistance of DUV photoresist, the designed SixOyNz is effective in imparting more etch resistance and suppressing metal substrate reflection. Excellent optical uniformity of the n, k and thickness d of the SixOyNz ARC is obtained with a manufacturable PECVD deposition process.

Effects of dielectric liners on TDDB lifetime of a Cu/ low-k interconnect

Thin films of silicon nitride (SiN) or silicon carbonitride (SiCN) were deposited as liners at metal-1 in a dual level metal Cu/organosilicate glass interconnect. Breakdown field and time dependent dielectric breakdown lifetime testing of comb/serpent test structures with SiN or SiCN liners showed improvements in performance, relative to a baseline no liner split. Two dimensional electric field simulations demonstrated that the dielectric liner significantly reduced the electric field at the Cu/OSG/etch stop interface.

Novel Diffusion Barrier with Ultra-Thin Silicon Nitride Cap Layer

A novel type of diffusion barrier, consisting of a conducting layer whose surface is enriched with silicon nitride, was developed. The new barrier was prepared by thermal decomposition of a metal-organic precursor, tetrakis(dimethylamino) titanium (TDMAT), followed by in-situ silane anneal and subsequent surface nitridation. It combines the conformality and conductivity advantages of the underlying diffusion barrier with the good barrier properties of silicon nitride. The new barrier films were characterized by sheet resistance measurement, secondary electron micrographs (SEM) and x-ray photoelectron spectroscopy (XPS). The thermal stability of Cu/capped barrier/Si multilayer structures was demonstrated.

ARC for sub-0.18 /spl mu/m logic and gigabit DRAM frontend and backend processes

We have developed different Si/sub x/O/sub y/N/sub z/ antireflective coating (ARC) films for many different substrates for deep-UV lithography and implemented then into sub-0.18 /spl mu/m logic and Gigabit DRAM frontend and backend processes. The Si/sub x/O/sub y/N/sub z/ film has dual functions: reducing substrate reflectivity to a minimum, and serving as a hardmask for poly and metal etch. These properties of Si/sub x/O/sub y/N/sub z/ are crucial to tight CD control and fabrication of unique device structures. Plasma damage from ARC deposition is negligible. Using the designed Si/sub x/O/sub y/N/sub z/ and linewidth reduction etch, sub-0.1 /spl mu/m metal gate nMOSFETs are demonstrated. Backend sub-0.25 /spl mu/m multilevel metal patterning and etch with Si/sub x/O/sub y/N/sub z/ produce excellent metal profiles and 100% comb yield. A designed ARC also produces superior 1 Gigabit DRAM 0.16 /spl mu/m storage node contact patterning.

Inorganic ARC for 0.18 /spl mu/m and sub-0.18 /spl mu/m multilevel metal interconnects

The accelerated control of critical dimensions (CD) in the sub-0.25 /spl mu/m region for semiconductor manufacturing has increased worldwide interest in the antireflective coating (ARC) process. In this paper, we report on a novel inorganic ARC design for deep-UV lithography and implementation of the ARC into multilevel metal interconnects for 0.18 /spl mu/m and sub-0.18 /spl mu/m technologies. The designed Si/sub x/O/sub y/N/sub z/ ARC not only reduces substrate reflectivity to a minimum and prevents DUV resist footing, but also serves as a hard mask for metal etch. Back-end-of-line (BEOL) sub-0.25 /spl mu/m multilevel metal patterning and etch with the Si/sub x/O/sub y/N/sub z/ ARC produced excellent metal profiles and 100% electrical comb yields. The designed ARC has also shown superior results to the conventional TiN metal ARC. The dielectric constant value is close to that of silicon oxide.

Dimensional metrology challenges for ULSI interconnects

Manufacturing of Ultra-Large-Scale-Integration (ULSI) semiconductor devices will likely require feature sizes as small as 150 nm by the year 2001, with an overlay accuracy of 55 nm, a critical dimension (CD) control of 12 nm and a precision of 2 nm. While this level of overlay control is currently achievable, the forecast CD control/precision present formidable metrology challenges for multilevel interconnects due to the high aspect ratios of scaled features as well as the introduction of new materials such as low-k dielectrics and copper. New techniques for edge detection, profile definition and film thickness measurement will be needed to meet future metrology needs.