Gregory B. Shinn

Chemical–mechanical polishing of SiOC organosilicate glasses: the effect of film carbon content

Abstract The effects of slurry chemistry and film properties on the chemical–mechanical polishing (CMP) of three organosilicate glasses (SiOC) were used to develop an understanding of the removal mechanism during SiOC CMP. The SiOC removal rate varied from 40 to 80 nm/min in slurries commonly used to polish silicon dioxide, with the removal rate increasing as the SiOC film carbon content decreased and the slurry pH increased. Film carbon content had the largest impact on CMP, due to its effect on film hydrophobicity and suppression of slurry chemical attack. SiOC surface roughness after CMP was as low as 0.15 nm at a slurry pH of 10.8 and 0.41 nm at a slurry pH of 6.0. Surface and bulk chemical measurements show that chemical reactions with the slurry during CMP occur only at the polymer surface and do not penetrate into the bulk of the films. Experimental results are compared to the CMP of SiLK 1 ‘silicon applications low-κ’ microelectronics resin, a polymer with a comparable dielectric constant, and, to a lesser degree, with silicon dioxide. A mechanism for the CMP of SiOC films in silicon dioxide polishing slurries is proposed that includes the effects of slurry chemistry and film properties.

Wafer-Scale Modeling of Pattern Effect in Oxide Chemical Mechanical Polishing

Dielectric film thickness variation arising from layout pattern dependency remains a major concern in oxide CMP. The severity of the pattern density effect is a function of the die location on the wafer, thus a combined wafer/die pattern dependent polishing model is required to fully assess the effectiveness of the process for a given planarization requirement. In this work, a two stage modeling methodology which accounts for both wafer-scale variation and within-die pattern dependencies, as well as their interaction, is developed. The effectiveness of the methodology is demonstrated over a range of polishing process conditions and consumable choices. We find that the integrated wafer/die CMP model accurately predicts the resulting increase or decrease in die-level pattern dependencies as a function of die position on the wafer.

Chemical mechanical planarization of multilayer dielectric stacks

Sub-0.5 micrometers multilevel metal schemes impose stringent requirements on both gap-fill and planarity of interlevel dielectrics. A variety of novel materials and processes are being investigated to meet these process requirements. In this paper, four dielectrics with good gap- filling capabilities are evaluated for planarity characteristics: SiO2 deposited using a high density plasma (HDP) with simultaneous deposition and sputtering, an organic spin-on-glass material SOG-A, an inorganic spin-on-glass material SOG-B, and SiO2 deposited using ozone and TEOS at sub-atmospheric pressure (SACVD). These materials are used for gap-fill followed by a capping layer of PETEOS. For global planarization, only the top layer of PETEOS is planarized using chemical mechanical polishing (CMP) without exposing the underlying gap-fill material. Planarization characteristics of the dielectric stacks are found to be significantly different, both before and after CMP. The CMP throughput is found to be very sensitive to the choice of the dielectric stack. For a given planarity goal, the CMP throughputs of three of the dielectric stacks are found to be significantly higher than that of a conventional single layer interlevel dielectric (ILD) consisting of only PETEOS.

Reliability Demonstration of a Ferroelectric Random Access Memory Embedded within a 130nm CMOS Process

Reliable operation of a 4 Mb ferroelectric random access memory (FRAM) embedded within a standard 130 nm CMOS process is demonstrated. Intrinsic endurance test to 5.4×1012 cycles shows no degradation of switched polarization. 10 year, 85degC, data retention life is demonstrated with 125°C data bake to 1,000 Hrs with no fails.

Reliability characterization of a Ferroelectric Random Access Memory embedded within 130nm CMOS

Reliability data is presented for a 4Mb Ferroelectric Random Access Memory (F-RAM) embedded within a 130nm CMOS process. Write/read endurance in the device exhibits stable intrinsic bit properties through 2.7x1013 cycles. Data retention demonstrates 10 year, 85°C operating life. No fails were observed with full-chip endurance test to 108 cycles followed by 1,000 hours of data retention bake at 125°C. Robust process reliability is demonstrated with no fails at 125°C operating life test.