Girish A. Dixit

Overview Of Process Integration Issues For Low K Dielectrics

The era of silicon Ultra-Large-Scale-Integration (ULSI) has spurred an everincreasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. Both interconnect resistance and capacitance play key roles in overall performance, but modeling simulations have highlighted the importance of reducing parasitic capacitance to manage crosstalk, power dissipation and RC delay. New dielectric materials with lower permittivity (k) are needed to meet this challenge. This paper summarizes the process integration and reliability issues associated with the use of novel low k materials in multilevel interconnects.

Integrated barrier/plug fill schemes for high aspect ratio Gb DRAM contact metallization

Abstract New contact fill integration schemes were developed for high aspect ratio Gb DRAM contact metallization. Integration schemes for both tungsten-plug contacts and aluminum-plug contacts were studied. For tungsten-plug contacts, various types of titanium liners and titanium nitride barriers were investigated and evaluated. These included collimated PVD (physical vapor deposition) titanium, ion metal plasma (IMP) titanium, and CVD (chemical vapor deposition) titanium liners; plasma enhanced CVD (PECVD) titanium nitride and plasma enhanced MOCVD (ECVD) titanium nitride barriers. The electrical results of 0.3 μm, 5:1 aspect ratio (AR) contact structures processed with a TiCl4-based CVD titanium liner and plasma enhanced CVD titanium nitride barrier show the lowest and the most tightly distributed contact parametrics. This is attributed to the conformal nature of the CVD process. In addition, the high titanium-deposition temperature, which leads to a simultaneous titanium silicide formation during the CVD titanium deposition process, may also have attribution to the low contact resistance and diode leakage obtained. In the case of aluminum-plug contacts, two different types of titanium nitride barriers (ECVD titanium nitride vs. silane-treated MOCVD titanium nitride) were evaluated and both showed comparable contact parametrics.

Chemical mechanical planarization of multilayer dielectric stacks

Sub-0.5 micrometers multilevel metal schemes impose stringent requirements on both gap-fill and planarity of interlevel dielectrics. A variety of novel materials and processes are being investigated to meet these process requirements. In this paper, four dielectrics with good gap- filling capabilities are evaluated for planarity characteristics: SiO2 deposited using a high density plasma (HDP) with simultaneous deposition and sputtering, an organic spin-on-glass material SOG-A, an inorganic spin-on-glass material SOG-B, and SiO2 deposited using ozone and TEOS at sub-atmospheric pressure (SACVD). These materials are used for gap-fill followed by a capping layer of PETEOS. For global planarization, only the top layer of PETEOS is planarized using chemical mechanical polishing (CMP) without exposing the underlying gap-fill material. Planarization characteristics of the dielectric stacks are found to be significantly different, both before and after CMP. The CMP throughput is found to be very sensitive to the choice of the dielectric stack. For a given planarity goal, the CMP throughputs of three of the dielectric stacks are found to be significantly higher than that of a conventional single layer interlevel dielectric (ILD) consisting of only PETEOS.

A Novel Process for Fabricating Conformal and Stable TiN‐Based Barrier Films

A new process for preparing TiN-based barrier films is reported. The process consists of thermal decomposition of a metallorganic precursor, tetrakis(dimethylamino)-titanium, followed by postdeposition annealing in silane ambient. Thin films fabricated using this approach have much higher stability and lower resistivity than those prepared using thermal decomposition alone. The new barrier films are conformal and exhibit good barrier performance for Al metallization.

Integrated CVD-PVD Al plug processing for sub-half micron features

Abstract We have successfully integrated Al plugs into a 0.25- μ m CMOS flow using two different chemical vapor deposition (CVD) Al metallization process schemes. Both process schemes utilized CVD Al grown from dimethyl aluminum hydride (DMAH) followed by physical vapor deposition (PVD) Al–Cu deposition at a wafer temperature of less than 400°C. One process consisted of a 600-A CVD Al liner followed by PVD Al–Cu and in situ reflow. The second process involved deposition of 2000 A of CVD Al to fill the vias and blanket PVD Al–Cu to provide copper doping. Analysis of morphology, texture, and grain size revealed a strong dependence on the nucleation layer, with Ti nucleation layers demonstrating the smoothest Al morphology and strongest Al(111) preferred orientation. While the CVD TiN layers yielded a larger grain size than the PVD layers, Al films on CVD TiN had a random grain orientation with no preferred texture. While the reflow process produced repeatable void-free fill on contacts and vias with aspect ratios >3:1, the blanket process was prone to occasional voiding. Mean via and contact resistances for wafers processed through a 0.25- μ m CMOS flow using the CVD–PVD reflow process were 1.91 Ω and 1.56 Ω, respectively, with lower resistance and tighter distributions than W in both cases. For the contact level process, reverse bias diode leakage was comparable to W. Based on the blanket film properties, robust fill, and electrical performance, the CVD Al/PVD Al–Cu reflow process is a potential replacement for the current W plug process.

Thermal stability of Al/barrier/TiSix multilayer structures

Abstract The thermal stability of Al–0.5% Cu/barrier/TiSi x multilayer structures is investigated. The barriers studied in this work are TiN films prepared by physical vapor deposition (PVD) and TiN-based barrier films prepared by metal–organic chemical vapor deposition (MOCVD) with post-deposition anneal in silane. Sheet resistance, secondary ion mass spectroscopy (SIMS), diode leakage current and high spatial resolution electron microscopy measurements show significantly better thermal stability for structures using the silane-treated MOCVD barrier. Structural and composition differences of the two types of barriers are examined.

Chemical Vapor deposition (CVD) TiN: a barrier metallization for submicron via and contact applications

A new technique for low temperature CVD TiN is introduced as a barrier/glue layer for sub 0.5 micron applications. Excellent conformity (> 70%) is achieved while maintaining good electrical performance and reliability. The films are shown to be polycrystalline TiN with no preferred grain orientation. In addition compositional analysis shows significant amounts of carbon in the film presumably between the grains. The electrical properties of the CVD film were evaluated at the via and contact level. The contact and via resistances of tungsten plugs using CVD TiN glue layers are shown to be comparable to plugs using sputtered TiN. The barrier performance of the film was also evaluated at the contact level. The superior junction leakage data indicate that the CVD TiN film should have wide application as a barrier metal for sub 0.5 mm applications.

Novel Diffusion Barrier with Ultra-Thin Silicon Nitride Cap Layer

A novel type of diffusion barrier, consisting of a conducting layer whose surface is enriched with silicon nitride, was developed. The new barrier was prepared by thermal decomposition of a metal-organic precursor, tetrakis(dimethylamino) titanium (TDMAT), followed by in-situ silane anneal and subsequent surface nitridation. It combines the conformality and conductivity advantages of the underlying diffusion barrier with the good barrier properties of silicon nitride. The new barrier films were characterized by sheet resistance measurement, secondary electron micrographs (SEM) and x-ray photoelectron spectroscopy (XPS). The thermal stability of Cu/capped barrier/Si multilayer structures was demonstrated.

0.25-μm multilevel interconnect with DUV processing

Decreasing critical dimensions and pitch at metal and hole levels requires the use of Deep-UV processing. Associated with this processing are issues of resist-substrate interactions, small process margins, and increasing aspect ratios forcing the modification of etch processes. In overcoming these issues at metal, we evaluate resist profiles on TiN, oxide hard mask, organic BARC and Ti metal. In all cases we see an improved profile when compared to resist on TiN. Electrical performance is compared in terms of linewidth, process linearity, and isolated to dense line bias for TiN, oxide hard mask, and Ti. Post etch electrical CD repeatability results are presented for TiN, Ti, and oxide. Cross section micrographs demonstrate consistent metal post etch profiles regardless of the metal stack. Results show the process is scaleable to 0.36 micrometers pitch metal. For hole patterning we see a major obstacle is achieving the required resolution capability with sufficient process latitude. We investigate the process margin for 0.25 micrometers contacts on BPSG substrates and the effect of pitch on the contact dimensions. Evaluation of the contacts after etch shows vertical sidewalls. The ability to extend the process to 0.20 micrometers is also explored. The results presented in this discussion demonstrate some of the issues and requirements for Deep-UV processing. With this technology we must explore the use of interfacial layers to overcome resist interactions with substrates and consider what might be non-standard processing to achieve desired results.

ARC for sub-0.18 /spl mu/m logic and gigabit DRAM frontend and backend processes

We have developed different Si/sub x/O/sub y/N/sub z/ antireflective coating (ARC) films for many different substrates for deep-UV lithography and implemented then into sub-0.18 /spl mu/m logic and Gigabit DRAM frontend and backend processes. The Si/sub x/O/sub y/N/sub z/ film has dual functions: reducing substrate reflectivity to a minimum, and serving as a hardmask for poly and metal etch. These properties of Si/sub x/O/sub y/N/sub z/ are crucial to tight CD control and fabrication of unique device structures. Plasma damage from ARC deposition is negligible. Using the designed Si/sub x/O/sub y/N/sub z/ and linewidth reduction etch, sub-0.1 /spl mu/m metal gate nMOSFETs are demonstrated. Backend sub-0.25 /spl mu/m multilevel metal patterning and etch with Si/sub x/O/sub y/N/sub z/ produce excellent metal profiles and 100% comb yield. A designed ARC also produces superior 1 Gigabit DRAM 0.16 /spl mu/m storage node contact patterning.