Eduardo Augusto Bezerra

Using the CAN protocol and reconfigurable computing technology for Web-based smart house automation

Abstract: This paper presents the hardware implementation of a multiplatform control system for house automation using FPGAs. Such a system belongs to a domain usually named domotics or smart house systems. The approach combines hardware and software technologies. The system is controlled through the Internet and the home devices being connected use the CAN control protocol. Users can remotely control their houses using a web browser (Client). Locally, instructions received from the Client are translated by the Server, which distributes the commands to the domestic appliances. The implemented system has the following characteristics, which distinguish it from existing approaches: (i) the client interface is automatically updated; (ii) a standard communication protocol (CAN) is used in the hardware implementation, providing reliability and error control; (iii) new appliances are easily inserted in the system; (iv) system security is provided by user authentication; (v) user rights can be set up by an administration interface.

A Reed-Solomon Algorithm for FPGA Area Optimization in Space Applications

This work describes an algebraic based design strategy targeting area optimization in reconfigurable computer technology (FPGA). Area optimization is a major issue as smaller components allow for better system adaptation, which is an expected feature of reconfigurable systems for space applications. The approach is applied in the design stage of a component for the communications module of an on-board computer system. The chosen component is a Reed-Solomon encoder, which has been implemented using a Hardware Description Language (VHDL) according to CCSDS recommendations, and targeting an FPGA platform. The paper investigates traditional alternatives for the encoder implementation, introduces the algebraic theory behind the proposed approach, describes the design process and discusses the area figures reached by the new design.

Optimizing HW/SW codesign towards reliability for critical-application systems

This work presents an innovative approach for hardware/software codesign of safety-critical computing systems. The proposed approach is based on system reliability requirements to decide which parts of the system are partitioned into hardware or software. The approach considers as input a complete software description of the design. In our case, we use as the initial description the C language and then, for those parts compiled to hardware, the Handel-C language is applied. After partitioning, we verify system reliability based on an adaptation of the weak mutation analysis technique. This technique was originally proposed for software testing by means of verifying the adequacy of a test vector set for a given program. We also present a case study in order to illustrate the proposed approach.

Analysis of SRAM-Based FPGA SEU Sensitivity to Combined Effects of Conducted EMI and TID

This work proposes a novel methodology to evaluate SRAM-Based FPGA SEU susceptibility to noise on VDD power pins and total-ionizing dose (TID). The procedure was demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8MV Pelletron accelerator, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. The injected noise on power supply bus comprised of voltage dips of 16.67% and 25% of VDD at two different frequencies 10Hz and 5kHz, and was performed according to the IEC 61.000-4-29 international standard.

Parallel Algebraic Approach of BCH Coding in VHDL

This work introduces an algebraic approach, using a Hardware Description Language (HDL) and shows that nowadays microelectronics technology could solve algebraic problems that were considered unsolvable using traditional sequential implementation forms as Berlekamp-Massey. An algebraic approach to implement Error Correcting Codes (ECC) is proposed, and implemented using a Hardware Description Language, specifically VHDL. The ECC designed for HDL algebraic implementation is Bose-Chaudhuri-Hocquenghem (BCH), that is one of the most important cyclic block codes. In this research work, we adopted n=63 and k=57, BCH(63,57) an usual configuration in many scientific communication systems as CCSDS telecommand systems of European Space Agency (ESA) and Agenda Espacial Brasileira (AEB). The achieved results clearly shows the main idea in our approach: to prove that an algebraic implementation is a far better approach, leading to an impressive efficiency, and much more suitable than any other sequential algorithm, even then the ones in a hardware version.

A Passive 915 MHz UHF RFID Tag

This paper describes the implementation of a passive RFID tag targeting low power implementation, which works on 915 MHz UHF frequency. The proposed architecture allows customizing the command sets implemented inside its digital block, according to the target application needs, saving area and reducing power consumption. A flexible design flow is proposed for the customization, verification and synthesis of the digital block, targeting low power requirements.

A Flexible Design Flow for a Low Power RFID Tag

This paper describes the implementation of a passive RFID tag targeting low power implementation, which works on 915 MHz UHF frequency. The proposed architecture allows customizing the command sets implemented inside its digital block, according to the target application needs, saving area and reducing power consumption. A flexible design flow is proposed for the customization, verification and synthesis of the digital block, targeting low power requirements.

Reliability verification of fault-tolerant systems design based on mutation analysis

We propose in this work an innovative approach for system reliability verification based on an adaptation of the weak mutation analysis technique. This technique was originally proposed for software testing by means of verifying the adequacy of a test vectors set for a given program. We also present a case study to illustrate the proposed approach. This methodology is being automated through the development of CAD tools that perform fault injection and simulation data analysis.

A 915 MHz UHF low power RFID tag

This paper describes the implementation of a passive low power tag, which works on 915 MHz UHF frequency. The tag implements an innovative and efficient synchronization algorithm, which deals with significant reference clock variations. A flexible design flow is proposed for the customization, verification and synthesis of the digital block, targeting low power requirements.

An adaptable educational platform for engineering and IT laboratory based courses

This work describes an educational kit developed at the University of Sussex, UK. The kit is based on reconfigurable computing technology, targeting its use in different laboratory based courses, with minimal modifications of the hardware components, and small GUI development. The paper describes the kit modules, and its adaptation to a case study.