José Carlos S. Palma

Remote and partial reconfiguration of FPGAs: tools and trends

This work describes the implementation of digital reconfigurable systems (DRS) using commercial FPGA devices. This paper has three main goals. The first one is to present the trend of DRS, highlighting the problems and solutions of each DRS generation. The second goal is to present in detail the configuration architecture of a commercial FPGA family allowing DRS implementation. The last goal is to present a set of tools for remote and partial reconfiguration developed for this FPGA family. Even though the tools are targeted to a specific device, their building principles may easily be adapted to other FPGA families, if they have an internal architecture enabling partial reconfiguration. The main contribution of the paper is the tool-set proposed to manipulate cores using partial reconfiguration in existing FPGA.

MAIA: a framework for networks on chip generation and verification

The increasing complexity of SoCs makes networks on chip (NoC) a promising substitute for busses and dedicated wires interconnection schemes. However, new tools need to be developed to integrate NoC interconnection architectures and IP cores into SoCs. Such tools have to fulfill three main requirements: (i) automated NoC generation; (ii) automated production of NoC-IP core interfaces; and (iii) seamless analysis of NoC traffic parameters. The objective of this paper is to present the MAIA framework, which includes functions to address all these requirements. NoCs generated by the MAIA framework have been used to successfully prototype SoCs in FPGAs.

Core communication interface for FPGAs

The use of pre-designed and pre-verified hardware modules, also called IP cores, is an important part of the effort to design and implement complex systems. However, many aspects of IP core manipulation are still to be developed. This paper presents an approach to solve problems related to the dynamic interconnection of hard IP cores. The approach targets system-on-a-chip designs build in a single FPGA device. The paper proposes a communication interface that allows IP core replacement during FPGA normal operation. The same interface also allows communication among distinct IP cores to take place.

Inserting Data Encoding Techniques into NoC-Based Systems

This work investigates the reduction of power consumption in networks-on-chip through the reduction of transition activity using data coding schemes. Power macromodels for NoC and encoding modules were built, allowing the estimation of the power consumption as a function of the transition activity at each module input. Power macromodels are embedded in a system model and a set of simulations are performed, analyzing the trade-off between the power savings due to coding schemes versus the power consumption overhead due to the encoding and decoding modules

Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation

This work addresses the problem of application mapping in networks-on-chip (NoCs). It explores the importance of characterizing network traffic to effectively predict NoC energy consumption. Traffic is seen as an important factor affecting the problem of mapping applications into NoCs having as goal to minimize the total dynamic energy consumption of a complex system-on-a-chip (SoC). Experiments showed that failing to consider the bit transitions influence on traffic inevitably leads to an energy estimation error. This error is proportional to the amount of bit transitions in transmitted packets. In applications that present a large number of packets exchange, the error is propagated, significantly affecting the mapping results. This paper proposes a high-level application model that captures the traffic effect and uses it to describe the behavior of applications. In order to evaluate the quality of the proposed model, a set of embedded systems were described using both, a previously proposed model (that does not capture the traffic effect), and the model proposed here. Comparing the resulting mappings, those derived from the proposed model showed improvements in energy savings with regard to the other model for all experiments

Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs

This work addresses the problem of application mapping in networks-on-chip (NoCs) having as goal to minimize the total dynamic energy consumption of a complex system-on-a-chip (SoC). It explores the importance of characterizing network traffic to predict NoC energy consumption and of evaluating the error generated when the bit transitions influence on traffic is neglected. This error is proportional to the amount of bit transitions in transmitted packets. The paper proposes a high-level application model that captures the traffic effect. In order to evaluate the quality of the proposed model, a set of real and random applications were described using both, a previously proposed model (that does not capture the traffic effect), and the model proposed here. Each high-level application model was implemented inside a framework that enables the description of different applications and NoC topologies description. The goal of this environment is to achieve mappings that reduce some NoC cost function. Comparing the resulting mappings, those derived from the model proposed here showed an average improvement of 45% in energy saving with regard to the other model.

Adaptive coding in networks-on-chip: transition activity reduction versus power overhead of the codec circuitry

This work investigates the reduction of power consumption in Networks-on-Chip (NoCs) through the reduction of transition activity using data coding schemes. The estimation of the NoC power consumption is performed with basis on macromodels which reproduce the power consumption on each internal NoC module according to the transition activity on its input ports. Such macromodels are embedded in a system model and a series of simulations are performed, aiming to analyze the trade-off between the power savings due to coding schemes versus the power consumption overhead due to the encoding and decoding modules.

Reducing the Power Consumption in Networks-on-Chip through Data Coding Schemes

This work investigates the reduction of power consumption in networks-on-chip (NoCs) through the reduction of transition activity using data coding schemes developed for bus-based systems and proposes a new coding scheme suitable for NoC-based systems. The estimation of the NoC power consumption was performed with basis on macromodels which reproduce the power consumption on each internal NoC module according to the transition activity on its input ports. Such macromodels were embedded in a system model and a series of simulations were performed, aiming to analyze the trade-off between the power savings due to coding techniques versus the power consumption overhead due to the encoding and decoding modules. The proposed coding scheme presented the best results for all of the simulated traffic patterns, when compared to other coding schemes found in the literature.

Evaluating the impact of data encoding techniques on the power consumption in networks-on-chip

This work addresses the problem of power consumption in networks-on-chip (NoCs). It investigates the reduction of dynamic power consumption through the reduction of transition activity using data coding techniques. Power macromodels for various NoC modules were built, allowing the estimation of the power consumption as a function of the transition activity at each modules inputs. Such macromodels were embedded in a system model and a series of simulations were performed, aiming to analyze the trade-off between the power savings due to coding techniques versus the power consumption overhead due to the encoding and decoding modules.

Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs

This work describes the implementation of digital reconfigurable systems (DRS) using commercial FPGA devices. The main goal is to present a set of tools for remote and partial reconfiguration developed for the Virtex FPGA family. Even though the tools are targeted to a specific device, their building principles may easily be adapted to other FPGA families, if they have an internal architecture enabling partial reconfiguration. The main contribution of the paper is the tool-set proposed to manipulate cores using partial reconfiguration in existing FPGAs.