Javier Valls

50 Years of CORDIC: Algorithms, Architectures, and Applications

Year 2009 marks the completion of 50 years of the invention of CORDIC (coordinate rotation digital computer) by Jack E. Volder. The beauty of CORDIC lies in the fact that by simple shift-add operations, it can perform several computing tasks such as the calculation of trigonometric, hyperbolic and logarithmic functions, real and complex multiplications, division, square-root, solution of linear systems, eigenvalue estimation, singular value decomposition, QR factorization and many others. As a consequence, CORDIC has been utilized for applications in diverse areas such as signal and image processing, communication systems, robotics and 3-D graphics apart from general scientific and technical computation. In this article, we present a brief overview of the key developments in the CORDIC algorithms and architectures along with their potential and upcoming applications.

The use of CORDIC in software defined radios: a tutorial

CORDIC is a versatile algorithm widely used for VLSI implementation of digital signal processing applications. This article presents a tutorial of how to use CORDIC to implement different communication subsystems that can be found in a software defined radio. Specifically, it shows how to use CORDIC to implement direct digital synthesizers, AM, PM, and FM analog modulators and ASK, PSK and FSK modulators, up-/down-converters of in-phase and quadrature signals, full mixers for complex signals, and phase detection for synchronizers. The article also shows some tricks to efficiently implement the algorithm

Evaluation of CORDIC Algorithms for FPGA Design

This paper presents a study of the suitability for FPGA design of full custom based CORDIC implementations. Since all these methods are based on redundant arithmetic, the FPGA implementation of the required operators to perform the different CORDIC methods has been evaluated. Efficient mappings on FPGA have been performed leading to the fastest implementations. It is concluded that the redundant arithmetic operators require a 4 to 5 times larger area than the conventional architecture and the speed advantages of the full custom design has been lost. That is due to the longer routing delays caused by the increase of the fan-out and the number of nets. Therefore, the redundant arithmetic based CORDIC methods are not suitable for FPGA implementation, and the conventional twos complement architecture leads to the best performance.

Low Cost Hardware Implementation of Logarithm Approximation

A low cost, high-speed architecture for the computation of the binary logarithm is proposed. It is based on the Mitchell approximation with two correction stages: a piecewise linear interpolation with power-of-two slopes and truncated mantissa, and a LUT-based correction stage that correct the piecewise interpolation error. The architecture has been implemented in an FPGA device and the results are compared with other low cost architectures requiring less area and achieving high-speed.

FPGA implementation of an IF transceiver for OFDM-based WLAN

The paper deals with the design and implementation on FPGA of an intermediate frequency transceiver for OFDM-based WLAN. The circuit has been particularized for the HIPERLAN/2 standard, but most of the work can be generalized to IEEE 802.11a/g standards. The system is composed of three main blocks (autocorrelator, CORDIC, and FFT processor) that are used in different time intervals to perform all the required operations. The autocorrelator is used for frame detection and carrier frequency offset estimation. The CORDIC is reused to estimate frequency offset, to compensate that frequency and to calculate the division in the channel estimation stage. Finally, the FFT/IFFT processor also uses its complex-number multiplier to perform the channel compensation of the received OFDM symbols. The whole IF transceiver fits in a low cost FPGA, an XC3S400-4 Spartan III device.

FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices

This paper presents a course on digital signal processing with field-programmable gate arrays (FPGA) devices. The course integrates two separate disciplines, digital signal processing (DSP) and very large scale integration (VLSI) design, and focuses on the development of a sophisticated DSP design from simulation to fixed-point implementation. The structure and methodology used in the proposed course are oriented to the design and implementation of an fast Fourier transform (FFT) spectrum analyzer. This application covers most topics included in a DSP course and gives better results that those obtained with typical courses performing independent multiple simple experiments. The project is divided into modules that show specific learning necessities and determine the course contents and organization. Each laboratory part is dedicated to design and implements the block of the analyzer related to the theoretical content presented in the class. At the end of the course the students have designed all the pieces in the DSP project and have completed and verified the system. The used methodology enables students and engineers to understand and develop complex fixed-point applications, looking for the best signal processing algorithms on hardware implementations, and also results in more motivated and active students.

Efficient mapping of CORDIC algorithms on FPGA

This paper presents a study of the efficient mapping on FPGA of the operators required to implement redundant arithmetic based CORDIC algorithms. It is shown that the redundant arithmetic operators require a 4 to 5 times larger area than the conventional ones. On the other hand, the speed advantages of the full-custom design has been lost, due to the longer routing delays caused by the increase of the fanout and the number of nets in the implementation of the redundant operators. Therefore, it is concluded that redundant arithmetic-based CORDIC methods are not suitable for implementation on FPGA.

Design and FPGA implementation of digit-serial FIR filters

In this paper the design of a family of digit-serial 8th-order FIR filters with programmable coefficients is presented. Both input data and coefficient size are 8 bits, but every filter of the family allows the computation with full precision of the intermediate data. The output data is truncated to 8 bits. The design of both, the digit-serial multiple precision multiply-and-accumulate and the digit-serial multiple-to-single precision converter, is detailed. All filters were implemented using an ALTERA FPGA being useful in applications with sample rate range from 5 to 22 MHz.

Non-Binary LDPC Decoder Based on Symbol Flipping with Multiple Votes

In this letter, a new algorithm to decode non-binary LDPC (NB-LDPC) codes is proposed. This algorithm is inspired from very low complexity decoders that have been proposed recently, in which only syndrome computations at the check node update are used, while performing symbol-flipping based update at the variable node. Usually, the low complexity decoders based on symbol flipping suffer from a non-negligible performance degradation compared to soft-decision NB-LDPC decoders. Our improved decoder makes use of a list of syndrome computations instead of a single one based on hard-decision, and builds soft information at the variable node input by assigning votes weighted by different amplitudes. Simulations show that using multiple votes with multiple weights yields better performance, while still maintaining the low complexity feature.

A study about FPGA-based digital filters

A set of operators suitable for digit-serial FIR filtering is presented. The canonical and inverted forms are studied. In each of these structures both the symmetrical and anti-symmetrical particular cases are also covered. All circuits have been implemented using an EPF10K50 Altera FPGA. The main results show that the canonical form presents less occupation and higher throughput. The 8-tap filter versions implemented can be applied in real-time processing with sample rate ranging up to 7 MHz using the bit-serial versions and up to 25 MHz with the bit-parallel ones.