Eduardo L. A. Macchione

Analysis of SRAM-Based FPGA SEU Sensitivity to Combined EMI and TID-Imprinted Effects

This work proposes a novel methodology to evaluate SRAM-based FPGAs susceptibility with respect to Single-Event Upset (SEU) as a function of noise on VDD power pins, TotalIonizing Dose (TID) and TID-imprinted effect on BlockRAM cells. The proposed procedure is demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8 MV Pelletron accelerator for the SEU test with heavy-ions, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. In order to observe the TID-induced imprint effect inside the BlockRAM cells, a second SEU test with neutrons was performed with Americium/Beryllium (241AmBe). The noise was injected into the power supply bus according to the IEC 61.000-4-29 standard and consisted of voltage dips with 16.67% and 25% of the FPGAs VDD at frequencies of 10 Hz and 5 kHz, respectively. At the end of the experiment, the combined SEU failure rate, given in error/bit.day, is calculated for the FPGAs BlockRAM cells. The combined failure rate is defined as the average SEU failure rate computed before and after exposition of the FPGA to the TID.

Heavy Ions Induced Single Event Upsets Testing of the 28 nm Xilinx Zynq-7000 All Programmable SoC

The recent advance of silicon technology has allowed the integration of complex systems in a single chip. Nowadays, Field Programmable Gate Array (FPGA) devices are composed not only of the programmable fabric but also by hard-core processors, dedicated processing block interfaces to various peripherals, on-chip bus structures and analog blocks. Among the latest released devices of this type, this work focuses in the 28 nm Xilinx Zynq-7000 All Programmable SoC (APSoC). While not immune to the radiation environment in space, the Zynq-7000 seems to be very attractive for the aerospace sector due to its high computational power capability and low-power consumption. In this work, results from heavy ions testing for Zynq-7000 are presented. The experiments were performed in a Brazilian facility located at the University of São Paulo, Brazil.

Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques

ARM processors are leaders in embedded systems, delivering high-performance computing, power efficiency, and reduced cost. For this reason, there is a relevant interest for its use in the aerospace industry. However, the use of sub-micron technologies has increased the sensitivity to radiation-induced transient faults. Thus, the mitigation of soft errors has become a major concern. Software-Implemented Hardware Fault Tolerance (SIHFT) techniques are a low-cost way to protect processors against soft errors. On the other hand, they cause high overheads in the execution time and memory, which consequently increase the energy consumption. In this work, we implement a set of software techniques based on different redundancy and checking rules. Furthermore, a low-overhead technique to protect the program execution flow is included. Tests are performed using the ARM Cortex-A9 processor. Simulated fault injection campaigns and radiation test with heavy ions have been performed. Results evaluate the trade-offs among fault detection, execution time, and memory footprint. They show significant improvements of the overheads when compared to previously reported techniques.

Analysis of SRAM-Based FPGA SEU Sensitivity to Combined Effects of Conducted EMI and TID

This work proposes a novel methodology to evaluate SRAM-Based FPGA SEU susceptibility to noise on VDD power pins and total-ionizing dose (TID). The procedure was demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8MV Pelletron accelerator, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. The injected noise on power supply bus comprised of voltage dips of 16.67% and 25% of VDD at two different frequencies 10Hz and 5kHz, and was performed according to the IEC 61.000-4-29 international standard.

First Successful SEE Measurements with Heavy Ions in Brazil

In this work, the first successful SEE measurements with heavy ions in Brazil is reported. The heavy ions were produced at the São Paulo 8 UD Pelletron accelerator. ¹²C, ¹⁶O, ¹⁹F, ²⁸Si, ³⁵Cl, ⁶³Cu and ¹⁰⁷Ag heavy ion beams were used to test a commercial off-the-shelf transistor. During irradiation, the response of a pMOS transistor was continuously monitored to measure the SEE events. In order to achieve a uniform low intensity beam the heavy ions were Rutherford scattered at 15⁰ by a 275 μg/cm² gold foil.

Analyzing the Influence of the Angles of Incidence and Rotation on MBU Events Induced by Low LET Heavy Ions in a 28-nm SRAM-Based FPGA

This paper shows the impact of low linear energy transfer heavy ions on the reliability of 28-nm Bulk static random access memory (RAM) cells from Artix-7 field-programmable gate array. Irradiation tests on the ground showed significant differences in the multiple bit upset cross section of configuration RAM and block RAM memory cells under various angles of incidence and rotation of the device. Experimental data are analyzed at transistor level by using the single-event effect prediction tool called multiscale single-event phenomenon prediction platform coupled with SPICE simulations.

Analysis of single-event upsets in a Microsemi ProAsic3E FPGA

The desirable use of Field-Programmable Gate Arrays (FPGAs) in aerospace & defense field has become a general consensus among IC and embedded system designers. Radiation-hardened (rad-hard) electronics used in this domain is regulated under severe and complex political and commercial treaties. In order to refrain from these undesired political and commercial barriers COTS FPGAs (despite the fact of their low reliability) have been considered as a promising alternative to replace rad-hard ICs. Moreover, SRAM-based FPGAs are pretermitted with respect to flash or anti-fuse devices. In this scenario, this paper analyses, by means of heavy-ion accelerator experiments, the Single-Event Upset (SEU) tolerance of the Microsemi ProAsic3E A3PE1500 COTS FPGA. This component is under pre-qualification process for use in some satellites of the Brazilian Space Program. Preliminary results are herein briefly presented and discussed. These experimental results allow us to consider this component as a strong candidate to replace rad-hard FPGAs, if its use is combined with strict system-level fault-tolerant strategies for error detection and correction.

Analyzing the influence of the angles of incidence on SEU and MBU events induced by low LET heavy ions in a 28-nm SRAM-based FPGA

This work highlights the impact of low LET heavy ions particles on the reliability of 28-nm Bulk SRAM cells from 4rtix-7 FPGA. Radiation tests showed significant differences in he MBU cross section of configuration (CRAM) and BRAM memory cells under various angles of incidence. Radiation results re compared with simulations at transistor level by using the ioft error tool, MUSCA SEP3 (MUlti-SCAle Single Event henomenon Prediction Platform) coupled with circuit imulations with the aim to analyze the differences of upset ensitivity as a function of layout SRAM. This analysis leads to etermine the correct layout and technology used in the tested PGA. By using the detailed classification of MBU events, it is ossible to analyze the effectiveness of correction mechanisms of he FPGA configuration memory.

Analysis of FPGA SEU sensitivity to combined effects of conducted EMI and TID

This work proposes a novel methodology to evaluate SRAM-Based FPGA SEU susceptibility to noise on VDD power pins and total-ionizing dose (TID). The procedure was demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8MV Pelletron accelerator, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. The injected noise on power supply bus comprised of voltage dips of 16.67% and 25% of VDD at two different frequencies 10Hz and 5kHz, and was performed according to the IEC 61.000-4-29 international standard.

Ionizing radiation effects on a COTS low-cost RISC microcontroller

Electronic system functionality degrades when these systems are operating in harsh environments, such as those where they are exposed to ionizing radiation. Understanding and measuring these effects is extremely important in order to design systems that can tolerate ionizing radiation. This work discusses experimental data of Heavy Ion and X-Ray radiation effects on a Commercial-Off-The-Shelf low-cost microprocessor. The heavy ions irradiation results suggest that, in this technology, the SRAM is more sensible to SEE than Flash memory. Ions with a LET higher than 5 MeV/mg/cm2 may cause the device to stop working.