Renato Giacomini

Trapezoidal Cross-Sectional Influence on FinFET Threshold Voltage and Corner Effects

Fin field effect transistors (FinFETS) are silicon-on-insulator (SOI) transistors with three-dimensional structures. As a result of some fabrication-process limitations (as nonideal anisotropic overetch) some FinFETs have inclined surfaces, which results in trapezoidal cross sections instead of rectangular sections, as expected. This geometric alteration results in some device issues, like carrier profile, threshold voltage, and corner effects. This work analyzes these consequences based on three-dimensional numeric simulation of several dual-gate and triple-gate FinFETs. The simulation results show that the threshold voltage depends on the sidewall inclination angle and that this dependence varies according to the body doping level. The comer effects also depend on the inclination angle and doping level.

Modeling Silicon on Insulator MOS Transistors with Nonrectangular-Gate Layouts

This work presents a new and simple approach for modeling silicon on insulator metal-oxide-semiconductor (MOS) dc characteristics for nonrectangular layout devices, based on decomposition of the original shape into trapezoidal parts and on an accurate but simple model of the trapezoidal layout transistor. Analytical expressions relating geometrical parameters and terminal current and voltages are presented for several shapes, such as L, U, T, and S, and other well-known devices such as the edgeless transistor and the asymmetric trapezoidal gate transistor. The proposed closed-form analytical expressions show good agreement with measured data and three-dimensional simulation results.

Illuminated to dark ratio improvement in lateral SOI PIN photodiodes at high temperatures

This work presents a study of the illuminated to dark ratio (IDR) of lateral SOI PIN photodiodes. Measurements performed on fabricated devices show a fivefold improvement of the IDR when the devices are biased in accumulation mode and under high temperatures of operation, independently of the anode voltage. The obtained results show that the doping concentration of the intrinsic region has influence on the sensitivity of the diodes: the larger the doping concentration, the smaller the IDR. Furthermore, the photocurrent and dark current present lower values as the silicon film thickness is decreased, resulting in a further increase in the illuminated to dark ratio.

Trapezoidal SOI FinFET analog parameters' dependence on cross-section shape

The trapezium is often a better approximation for the FinFET cross-section shape, rather than the design-intended rectangle. The frequent width variations along the vertical direction, caused by the etching process that is used for fin definition, may imply in inclined sidewalls and the inclination angles can vary in a significant range. These geometric variations may cause some important changes in the device electrical characteristics. This work analyzes the influence of the FinFET sidewall inclination angle on some relevant parameters for analog design, such as threshold voltage, output conductance, transconductance, intrinsic voltage gain (AV), gate capacitance and unit-gain frequency, through 3D numeric simulation. The intrinsic gain is affected by alterations in transconductance and output conductance. The results show that both parameters depend on the shape, but in different ways. Transconductance depends mainly on the sidewall inclination angle and the fixed average fin width, whereas the output conductance depends mainly on the average fin width and is weakly dependent on the sidewall inclination angle. The simulation results also show that higher voltage gains are obtained for smaller average fin widths with inclination angles that correspond to inverted trapeziums, i.e. for shapes where the channel width is larger at the top than at the transistor base because of the higher attained transconductance. When the channel top is thinner than the base, the transconductance degradation affects the intrinsic voltage gain. The total gate capacitances also present behavior dependent on the sidewall angle, with higher values for inverted trapezium shapes and, as a consequence, lower unit-gain frequencies.

Fin shape influence on the analog performance of standard and strained MuGFETs

From the analog performance perspective, there is a fin cross-section shape influence on electric parameters. At weak inversion levels the gm/ID is shape dependent, while for moderate and strong inversions the strain type is dominant, where the mobility starts to play an important role. The output conductance and the Early voltage show a strong dependence on both fin shape and strain type. For thinner Wmid there is a performance increase of up to 3 dB on intrinsic voltage gain compared to rectangular shape. Strained devices present better AV and fT, both following the gm tendency for each channel length.

A Commercial off-the-shelf pMOS Transistor as X-ray and Heavy Ion Detector

Recently, p-channel metal-oxide-semiconductor (pMOS) transistors were suggested as fit for the task of detecting and quantifying ionizing radiation dose. Linearity, small detection volume, fast readout, portability, low power consumption and low radiation attenuation are some of the pMOS advantages over PIN diode and thermoluminiscent dosimeters. A hand-held measurement system using a low power commercial off-the-shelf pMOSas the sensor would have a clear advantage due to the lower cost incurred by a standard technological process. In this research work, we tested the commercial device 3N163 regarding its behaviouras an X-ray sensor, as well as its possible application as a heavy-ion detector. To study the radiation effects of X-rays, a XRD-7000 (Shimadzu) X-ray diffraction setup was used to produce 10-keV effective energy photons. Heavy ions tests involved 12C, 16O, 19F, 28Si, 35Cl, 63Cu and 107Ag beams scattered at 15° by a 275 μg/cm2 gold target, which provide LETs (Linear Energy Transfer) from 4 to 40 MeV/mg/cm2. The signal readout was done using a 1 GHz oscilloscope with a 10-Gsamples/s conversion rate, high enough to permit the recording of transient pulses in the drain current. In this case, an ion can cause a current signal proportional to the ion beam used. Through this study it was found that a simple commercial pMOS device can be reliably used as a detector of X-rays as well as heavy ion detector.

Transitory recovery time of bio-potential amplifiers that include CMOS pseudo-resistors

In this paper a study of the recovery time after a high-amplitude input transitory voltage is evaluated, for a low-frequency bio-potential amplifier. The importance of this parameter for very small low frequency cut-off circuits relies on the expectation, given by the linear model, that the amplifier may take hundreds of seconds to come out of the saturation state, what could be unacceptable for real applications. Actually, the nonlinearity of some components that are used in the amplifiers feedback circuit, particularly the CMOS pseudo-resistors, contributes to the reduction of the recovery time. The bio-amplifier evaluation was carried out using a typical two-stage circuit topology. The circuit behavior is evaluated for several CMOS pseudo-resistor values, with nMOS and pMOS solutions, using a new pseudo-resistor non-linear model. The frequency response target is a 10KHz bandwidth with low frequency cutoff of 1Hz (-3dB). The behavior was evaluated using a MOSIS SCN05 technology (0.5μm) and BSIM3V3.1 models on Eldo™ SPICE analog simulator.

Sensing magnetic fields in any direction using FinFETs and L-gate FinFETs

The best-explored integrated magnetic field sensors are built with planar IC technologies, which do not allow 3D sensing in standard fabrication processes due to their bi-dimensional nature. Unlike planar devices, FinFETs can be used to sense magnetic fields in any direction. This work proposes and evaluates the use of FinFETs as magnetic sensors. The sensibility of FinFET differential arrays to lateral and vertical magnetic fields is quantified. This work also proposes the L-shaped gate, to improve the sensor performance.

An analytical estimation model for the spreading resistance of Double-Gate FinFETs

The FinFET spreading resistance is the component of the parasitic resistance of FinFETs caused by the curved shape of the current lines in drain and source regions, close to the junctions. This work proposes a very simple analytical model for the spreading resistance of Double-Gate FinFETs that is valid for any fin width from 16nm, without fitting parameters. The model output was compared to data extracted from numeric simulation and it showed accuracy better than 8% for the considered range of devices with three different doping concentrations.

An accurate closed-expression model for FinFETs parasitic resistance

Abstract A new closed-expression analytic model for parasitic resistance of FinFETs (Fin-Field-Effect-Transistors), which allows a fast estimation of this parasitic element, is proposed and evaluated in this work. The parasitic resistance is one of the most significant parameter for performance and reliability degradations in scaled devices. The model is based in the current distribution observed in three-dimensional simulations and is very accurate when compared to experimental data. The contact resistance was modeled using a variable impedance transmission line model, to approximate source and drain geometries to the real shapes of these regions. The model has a closed expression, without adjustment parameters. All results were compared with two previous models presented in literature, and the proposed model was the one which presented the best accuracy: percent errors below 10% for different source and drain doping concentrations, contact lengths, extension lengths, contact resistivity and fin widths.