Eduardo Maayan

4-bit per cell NROM reliability

The realization of a 4-bit NROM cell is possible due to the two physically separated bits on each side of the cell. Only 4 Vt levels on each bit are required. Key features of a 4-bit product are optimized technology, accurate and fast programming algorithm (3MB/s write speed), no single bit failures and window sensing with moving reference as an error detection and correction scheme

Advancement in Charge-Trap Flash memory technology

Charge-trap Flash memory has been successfully productized in high volume for several technology generations. Two-bits-per-cell MirrorBit® charge-trap technology has been the industry benchmark for NOR Flash for more than a decade, spanning six generations of scaling. More recently Heterogeneous Charge Trap (HCT)™ NAND Flash as well as embedded Charge Trap (eCT)™ NOR Flash have been developed. The planar cell structures will enable continued scaling of these charge-trap technologies, while new architectures such as 3D charge-trap Flash will emerge and further extend the density-growth trend.

A 4b/cell NROM 1Gb Data-Storage Memory

A 4b/cell 1Gb data flash based on a low-cost NROM process technology is achieved. The design includes a two-phase programming algorithm for supporting a fast and accurate threshold-voltage control. The read scheme incorporates a simple error-detection mechanism combined with an accurate drain-side sensing circuit with a built-in offset cancellation

A 4b/Cell 8Gb NROM Data-Storage Memory with Enhanced Write Performance

The increasing demand for cost reduction of data storage solutions calls for both cell-size shrink, as well as compressing more bits of data into the storage element. Yet the low cost solution is required to have fast enough write operation to fit density-hungry applications. An 8 Gb data flash storage device based on 4b/cell NROM technology is presented in this paper. A major improvement in write time is accomplished through improvement of programming techniques, erase scheme and sensing methods.

A 55 mm/sup 2/ 256 Mb NROM flash memory with embedded microcontroller using an NROM-based program file ROM

A 256 Mb flash memory based on 2 b/cell 0.17 /spl mu/m NROM technology supports 90 ns random read access, 66 MHz synchronous read, and 3 /spl mu/s/word programming. This 55 mm/sup 2/ device includes an 8 b embedded microcontroller for program and erase operations, power-up sequence, BIST, and more. The microcontroller executes its code from an NROM-based embedded ROM, performing 30 ns/word read access.