Orest Bula

Ultralow-power SRAM technology

An ultralow-standby-power technology has been developed in both 0.18-µm and 0.13-µm lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage six-transistor (6T) SRAM cell sizes are 4.81 µm2 and 2.34 µm2, corresponding respectively to the 0.18-µm and 0.13-µm design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25°C and is less than 400 fA per cell at 1.5 V, 85°C. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the well-known gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.

The use of simulation in semiconductor technology development

Abstract An overview is presented on the types of problems encountered in semiconductor technology development that are actively studied today via simulation methods. Most of the simulation examples presented here are ones that have been explicitly used in actual industrial semiconductor device design cycles to aid in the optimization of device structures. The examples described here include process simulations, such as the diffusion of dopant atoms, oxidation, etching, deposition, and epitaxial growth, as well as device simulations, which predict the flow of charge carriers and field distribution within a semiconductor device, given its material structure and operating conditions. The main aim here is to illustrate, by example, some of the capabilities of state-of-the-art simulators used in characterizing and predicting semiconductor process and device-related phenomena. We will attempt to outline the degree of sophistication of the physics incorporated in such simulation programs, and provide some contrast to the fundamental physics required for a complete physical description. As will be indicated, simulation development necessarily involves molding the appropriate physical models and numerical algorithms into a package that can be handled in a reasonable length of time by modern computing systems. We briefly outline some of the advances that have been made, and some concerns that remain, in such simulation development.

Aids for driving lithography hard: wafer-level process control features

This paper investigates the design of targets for in-line lithography process control. The need for wafer-level understanding and control of defocus has driven the development of several of methods for detecting focus shifts. The methods are typically based on measurements of line-end shortening and use optical methods. This work starts a dual-tone pair of arrays, one built from resist lines and the other from resist troughs. These process control targets area also known as schnitzls. The influence of the shape of the individual lines, the line pitch and separation of arrays are investigated using both simulations and wafer resist CDSEM measurements. A theoretical model was applied to all data to enable objective comparison of different designs. A guide to dose and defocus target design for process window monitoring is provided as part of the summary.

Pushing SRAM densities beyond 0.13-μm technology in the year 2000

For any given technology in the logic foundry business it is highly desirable to offer a dense SRAM design which can be manufactured using the same mask and wafer toolsets as the base design. This paper discusses the lithographic issues related to imaging a pseudo-0.11 um technology within a 0.13 um ground rule, including optical proximity correction, design, mask making issues, and comparison of top-down SEM to simulation. To achieve a dense SRAM and quick turn around on design shrinks, simulation and experimental feedback are key. In this study, SRAM cells were redesigned, and a well calibrated resist and etch bias model, in conjunction with a fast micro lithographic aerial image simulator and mask model, were used to predict and optimize the printed shapes through all critical levels. One of the key issues is the ability to correlate and feedback experimental data into the resist simulation. Experimental results using attenuated phase shift masks and state-of-the-art resist process technology are compared to the simulation.