Egor S. Sogomonyan

On-line fault detection and location for NoC interconnects

A novel method for on-line fault detection and location in network-on-chip (NoC) communication fabrics is introduced. This approach is able to distinguish between faults in the communication links and faults in the NoC switches. The idea is based on the use of code-disjoint routing elements, combined with parity check encoding for the inter-switch links. We analyze the effect of our method on relevant performance parameters - power, latency, and throughput. Experiments show that our approach is effective and requires minimal modifications of the existing design methods for NoC interconnects

A new code-disjoint sum-bit duplicated carry look-ahead adder for parity codes

A new code-disjoint self-checking carry look-ahead adder is proposed. To reduce the necessary area and the power dissipation only the sum bits of the adder cells are duplicated. This is possible since the input parity is determined by use of internal nodes of the adder cells. The adder is modeled by a SYNOPSIS CAD tool from the EUROCHIP-Project with a standard library. With respect to duplication and comparison the necessary area and the power dissipation can be reduced up to 38 % and up to 29 % respectively compared to an increase of the maximal delay of only 12 %.

Early error detection in systems-on-chip for fault-tolerance and at-speed debugging

In this paper we propose a new method for the design of duplex fault-tolerant systems with early error detection and high availability. All the scannable memory elements (flip-flops) of the duplicated system are implemented as multimode memory elements according to Singh et al. (1999), thus allowing during normal operation the accumulation of a signature of its states in its scan-paths. By continuously comparing a 1-bit sequence of the compacted scan-out outputs of the accumulated signatures of the duplicated systems an error can be already detected and a recovery procedure started before an erroneous result appears at the system outputs when a computations is completed. The accumulation of a signature during normal operation can also be used for debugging at-speed. For this application the system need not be duplicated.

Self-checking code-disjoint carry-select adder with low area overhead by use of add1-circuits

In this paper, a new code-disjoint totally self-checking carry-select adder, with low area overhead, is proposed which is based on the simplified design of carry-select adders by use of add1-circuits as proposed in (T. Y. Chang et al., IEE Elec. Lett., vol.34, no.22, p.2101-2103, 1998) and (Y. Kim et al., ISCAS, p.218-221, 2001). The area overhead for the proposed adder is only 40% of a traditional carry-select adder without error detection.

A new totally error propagating compactor for arbitrary cores with digital interfaces

In this paper a new totally error propagating compactor is proposed which can be used for arbitrary core-based designs and also for mixed signal ICs with digital interfaces. All errors at the outputs of the cores are detected at the outputs of the proposed compactor. This property is achieved with a small amount of time redundancy.

A structural approach for space compaction for concurrent checking and BIST

In this paper a new structural method for linear output space compaction is presented. The method is applicable to concurrent checking and built-in self test (BIST). Based on simple estimates for the probabilities of the existence of sensitized paths from the signal lines to the circuit outputs output partitions are determined without fault simulation. For all ISCAS 85 benchmark circuits three groups of compacted outputs are sufficient to achieve 100% fault coverage in test mode and for 3 to 5 groups an error detection probability of 98% is obtained in on-line mode. The method can be applied to very large circuits.

New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors

In this paper, a new self-checking code-disjoint Booth-2 multiplier with an improved error detection and with a reduced area overhead is proposed. Compared to the 64 times 64 multiplier without error detection the area for the proposed multiplier increases for the different implementations only by 23%-30%. Especially for soft errors the error detection capability is significantly improved. All even or odd (soft) errors in the output registers are detected

A new self-checking multiplier by use of a code-disjoint sum-bit duplicated adder

In this paper a new self-checking multiplier which consists of an AND-matrix, a carry-save adder and a final sumbit duplicated adder is proposed. The AND-matrix and the carry-save adder are parity checked. All errors due to single stuck-at faults in the combinational part and all even or odd (soft) errors in one of the duplicated output registers are detected. The parity checked carry-save adder is implemented by use of carry-dependent sum adder cells with a single carry-out signal. Compared to a corresponding multiplier without error detection the necessary area is about 125% to 135%.

A modulo p checked self-checking carry select adder

In this paper a new self-checking carry select adder is proposed. The duplicated adder blocks which are inherent to a carry select adder without error detection are checked modulo 3. Compared to a carry select adder without error detection the delay of the MSB of the sum of the proposed adder does not increase. Compared to a self-checking duplicated carry select adder the area is reduced by 20%. No restrictions are imposed on the design of the adder blocks.

Partially duplicated code-disjoint carry-skip adder

In this paper a new self-checking code-disjoint partially duplicated fast carry-skip adder is proposed which is for 64 bits the fastest self-checking adder known so far. For the first time the adder cells of a fast carry-ripple adder are used for the design of a carry-skip adder. The propagate signals are implemented only once. They are utilized to compute the duplicated sum bits and simultaneously to check the input parity and some internal XOR-gates.