Daniel Marienfeld

Self-checking code-disjoint carry-select adder with low area overhead by use of add1-circuits

In this paper, a new code-disjoint totally self-checking carry-select adder, with low area overhead, is proposed which is based on the simplified design of carry-select adders by use of add1-circuits as proposed in (T. Y. Chang et al., IEE Elec. Lett., vol.34, no.22, p.2101-2103, 1998) and (Y. Kim et al., ISCAS, p.218-221, 2001). The area overhead for the proposed adder is only 40% of a traditional carry-select adder without error detection.

New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors

In this paper, a new self-checking code-disjoint Booth-2 multiplier with an improved error detection and with a reduced area overhead is proposed. Compared to the 64 times 64 multiplier without error detection the area for the proposed multiplier increases for the different implementations only by 23%-30%. Especially for soft errors the error detection capability is significantly improved. All even or odd (soft) errors in the output registers are detected

A new self-checking multiplier by use of a code-disjoint sum-bit duplicated adder

In this paper a new self-checking multiplier which consists of an AND-matrix, a carry-save adder and a final sumbit duplicated adder is proposed. The AND-matrix and the carry-save adder are parity checked. All errors due to single stuck-at faults in the combinational part and all even or odd (soft) errors in one of the duplicated output registers are detected. The parity checked carry-save adder is implemented by use of carry-dependent sum adder cells with a single carry-out signal. Compared to a corresponding multiplier without error detection the necessary area is about 125% to 135%.

A modulo p checked self-checking carry select adder

In this paper a new self-checking carry select adder is proposed. The duplicated adder blocks which are inherent to a carry select adder without error detection are checked modulo 3. Compared to a carry select adder without error detection the delay of the MSB of the sum of the proposed adder does not increase. Compared to a self-checking duplicated carry select adder the area is reduced by 20%. No restrictions are imposed on the design of the adder blocks.

Partially duplicated code-disjoint carry-skip adder

In this paper a new self-checking code-disjoint partially duplicated fast carry-skip adder is proposed which is for 64 bits the fastest self-checking adder known so far. For the first time the adder cells of a fast carry-ripple adder are used for the design of a carry-skip adder. The propagate signals are implemented only once. They are utilized to compute the duplicated sum bits and simultaneously to check the input parity and some internal XOR-gates.

A new self-checking sum-bit duplicated carry-select adder

In this paper the first code-disjoint totally self-checking carry-select adder is proposed. The adder blocks are fast ripple adders with a single NAND-gate delay for carry-propagation per cell. In every adder block both the sum-bits and the corresponding inverted sum-bits are simultaneously implemented. The parity of the input operands is checked against the XOR-sum of the propagate signals. For 64 bits area and maximal delay are determined by the SYNOPSYS CAD tool of the EUROCHIP project. Compared to a 64 bit carry-select adder without error detection the delay of the most significant sum-bit does not increase. The area is 170% of a 64 bit carry-select adder (without error detection and not code-disjoint).

A new self-checking code-disjoint carry-skip adder

In this paper the first self-checking code-disjoint carry-skip adder is investigated The adder is code-disjoint with respect to the parity encoded operands and self-testing and fault-secure with respect to all single stuck-at faults of the adder cells.

A new self-checking and code-disjoint non-restoring array divider

In this paper a new code-disjoint self-checking non-restoring array divider is proposed. The divider array which is designed by use of different carry-dependent sum-adder cells is parity checked. Only a single carry-out signal per adder cell is needed. Both the output registers for the dividend and for the remainder are (inverted) duplicated to guarantee a high coverage for soft errors. For the first time also the final correction adder is concurrently checked. Non-restoring array dividers for 8-bit, 16-bit and 32-bit dividends are designed by use of the SYNOPSYS tools by EUROPRACTICE. Compared to a non-restoring array divider without error detection the area overhead is about 30 % and the additional delay is only from 2% to 11 %

Modulo p = 3 Checking for a Carry Select Adder

In this paper a self-checking carry select adder is proposed. The duplicated adder blocks which are inherent to a carry select adder without error detection are checked modulo 3. Compared to a carry select adder without error detection the delay of the MSB of the sum of the proposed adder does not increase. Compared to a self-checking duplicated carry select adder the area is reduced by 20%. No restrictions are imposed on the design of the adder blocks.