Shengchang Cai

A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization

While analog-to-digital converter (ADC)-based serial link receivers enable powerful digital equalization for high data rate operation, the ADC and digital equalization power consumption is a key concern in applications that support operation over a wide range of channels with varying amounts of intersymbol interference (ISI). This paper presents a hybrid ADC-based receiver architecture which employs a 3-tap analog feed-forward equalizer (FFE) embedded inside a 6 bit asynchronous successive approximation register (SAR) ADC and a per-symbol dynamically enabled digital equalizer, resulting in both reduced equalizer complexity and power consumption. Fabricated in general purpose (GP) 65 nm CMOS, the hybrid ADC-based receiver occupies 0.81 mm2 area. 10 Gb/s operation is verified for FR4 channels with up to 36.4 dB attenuation, with the proposed dynamic enabling of the digital 4-tap FFE and 3-tap decision feedback equalizer (DFE) on a per-symbol basis resulting in nearly 30 mW savings and an overall receiver power less than 90 mW.

A 25GS/s 6b TI binary search ADC with soft-decision selection in 65nm CMOS

A 25GS/s 8-way time-interleaved binary search ADC employs a novel soft-decision selection algorithm to improve metastability tolerance and relax T/H settling requirements. The T/H design is further relaxed with reduced loading from a new shared-input three comparator structure. Fabricated in GP 65nm CMOS, the ADC achieves 4.62-bits ENOB at Nyquist and 143 fJ/conv.-step FOM, while consuming 88mW and occupying 0.24mm2 core ADC area.

3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS

ADC-based receivers are currently being proposed in high-speed serial link applications to enable flexible, complex, and robust digital equalization in order to support operation over high loss channels [1-3]. However, the power dissipation of the ADC, as well as the digital equalization that follows, is a major concern for wireline receiver applications [3]. In this work, a hybrid ADC-based receiver architecture is presented that introduces innovations in both the ADC and the digital equalizer design. First, an analog 3-tap feed-forward equalizer (FFE) is efficiently embedded into a 6b time-interleaved SAR ADC, allowing for reductions in both ADC resolution and digital equalizer complexity. Second, significant power reduction is achieved by detecting reliable symbols at the ADC output and dynamically enabling/disabling the digital equalizer.

Statistical modeling of metastability in ADC-based serial I/O receivers

This paper develops metastability error models for flash and asynchronous SAR ADCs and describes a novel ADC-based receiver statistical modeling methodology to analyze the BER performance impact of metastability error propagation through digital FFE equalization.

Adaptively-tunable RF photonic filters

The emergence of silicon photonics has enabled potential implementations of RF photonic filters with the size, weight, and power requirements of radio systems with small form factors. This paper presents a fourth-order elliptic digital filter designed in the optical domain with all-pass filter (APF) unit cells. A monitor-based adaptive tuning algorithm is proposed to calibrate the optical filter response with high accuracy and provide rapid filter reconfiguration.

A 32 Gb/s ADC-based PAM-4 receiver with 2-bit/stage SAR ADC and partially-unrolled DFE

A PAM-4 ADC-based receiver employs a 32-way time-interleaved 6-bit 2-bit/stage loop-unrolled SAR ADC with a single capacitive reference DAC. Digital equalization complexity is reduced with a new PAM-4 DFE architecture that has a gate count comparable to an NRZ DFE, while simultaneously halving the critical path delay. A 3-tap FFE is embedded in the ADC using an additional non-binary DAC to improve the coverage of the 6-bit FFE coefficient space. This 3-tap embedded FFE and CTLE front-end partial equalization allows placement of the CDRs Mueller-Muller phase detector directly at the ADC output to avoid excessive loop delay. Fabricated in GP 65nm CMOS, the 32Gb/s receiver operates at a BER < 10−11 with a 27 dB loss channel and < 10−9 with a 30 dB loss channel without utilizing any transmit equalization. The complete ADC-based receiver achieves a power efficiency of 8.25pJ/bit, including all the front-end, ADC, and DSP power.

A 25 GS/s 6b TI Two-Stage Multi-Bit Search ADC With Soft-Decision Selection Algorithm in 65 nm CMOS

While high-speed analog-to-digital converter (ADC) front-ends in serial link receivers enable flexible and powerful digital signal processing-based (DSP-based) equalization, the robustness and power consumption of these ADCs can limit overall receiver energy efficiency. This paper presents a 25 GS/s 6b 8-way time-interleaved multi-bit search ADC that employs a soft-decision selection algorithm to relax track-and-hold (T/H) settling requirements and improve ADC metastability tolerance. T/H bandwidth is also improved with a new shared-input double-tail three-latch structure. Fabricated in general purpose 65 nm CMOS, the ADC occupies 0.24 mm2 total area. A signal-to-noise and distortion ratio (SNDR) of 29.6 dB is achieved at Nyquist while consuming 88 mW from a 1 V supply, translating into a figure-of-merit of 143 fJ/conversion step. A measured <10

Automatic monitor-based tuning of reconfigurable silicon photonic 2 nd -order APF-based pole/zero filters

^{-10}

Comprehensive adaptive tuning of silicon RF photonic filters

metastability error rate demonstrates the effectiveness of the soft-decision selection algorithm.