Eiji Ikawa

A capacitor-over-bit-line (COB) cell with a hemispherical-grain storage node for 64 Mb DRAMs

A novel capacitor-over-bit-line (COB) cell with a hemispherical-grain (HSG) poly-Si storage node has been developed. This memory cell provides large storage capacitance by increasing the effective surface area of a simple storage node and is manufacturable by optical delineation. The feasibility of the COB cell for 64-Mb DRAMs has been verified by a 64-kb test memory with 1.8- mu m/sup 2/ cells using a 0.4- mu m design rule, storage capacitance of 30 fF, 7-nm-SiO/sub 2/-equivalent dielectric film, and a storage node height of 0.5 mu m.<<ETX>>

Low-energy electron energy loss spectroscopy of Cl adsorbed Si(111), Si(100) and Si(110) surfaces

Abstract The chlorine adsorption on Si(111)7×7, Si(100)2×1 and Si(110)16×2 surfaces is studied by low-energy electron energy loss spectroscopy (LEELS), Auger electron spectroscopy (AES) and reflection high energy electron diffraction (RHEED). Different primary electron energies are employed on the EELS measurement to vary the probing depth. The Cl/Si(111) surface shows one conspicuous LEELS peak which is related to the Cl(p z ) state, which forms a σ-like bonding state with the Si(p z ) state. The Cl/Si(100) surface shows two LEELS peaks presenting different depth profiles, which are thought to be related to the Cl(p z ) bonding state and to the Cl(p x , p y ) state, which forms a π-like bonding state. The difference of the LEELS spectra for different substrate orientations is attributable to different adsorption configurations; whereas Cl adatoms sit obliquely on Si atoms on the Si(100) and Si(110) surfaces, Cl adatoms sit on top of Si atoms on the Si(110) surface. The AES and RHEED results to the speculation that Cl adsorption does not function to resolve surface dimers but occurs, at dangling bonds on surface Si atoms and on steps.

A quarter-micrometer interconnection technology using a TiN/Al-Si-Cu/TiN/Al-Si-Cu/TiN/Ti multilayer structure

An interconnection structure using a TiN/Al-1% Si-0.5% Cu/TiN/Al-1% Si-0.5% Cu/TiN/Ti multilayer conductor was investigated as a quarter-micrometer interconnection candidate for 256-Mb DRAMs. It was found that intermetallic compounds such as TiAl/sub x/ were formed at both grain boundaries of Al-Si-Cu and interfaces between Al-Si-Cu and TiN of the multilayer, resulting in both increase in Vickers hardness and suppression of stress relaxation. The multilayer conductor strip, which was covered with plasma-enhanced chemical vapor deposition silicon nitride (P-SiN), suppressed stress-induced voiding after heat treatment at 500 degrees C. Electromigration tests for quarter-micrometer wide multilayer strips indicated the improvement in the mean time to failure and the increase of the standard deviation. >

New stacked capacitor structure using hemispherical-grain polycrystalline-silicon electrodes

A new technology which makes storage electrode surfaces uneven has been developed for realizing 64 Mbit dynamic random access memories (DRAMs). This technology utilizes a Si film which is deposited by low‐pressure chemical vapor deposition at 550 °C and has hemispherical grains (HSG). The surface area of the HSG‐Si film is about twice as large as Si films deposited at other temperatures. The specific temperature, 550 °C, corresponds to the transition temperature of the film structure from amorphous to polycrystalline. By applying the HSG‐Si film as the storage electrode of a stacked capacitor, a capacitance of twice the value is obtained. The increase of the capacitance makes it possible to reduce the DRAM cell area, even by using a relatively thick dielectric film, thereby providing higher reliability.

Wafer Treatment Using Electrolysis-Ionized Water

Electrolysis-ionized water treatment is shown to be useful for removing polystyrene particles from contact holes, silicon surface cleaning and the removal of metal contamination such as copper. Electrolysis-ionized water has a controllable pH and a higher oxidation-reduction potential than chemicals. Moreover, this water does not contain acid or alkaline chemicals, and can easily be neutralized without adding chemicals. Electrolysis-ionized water treatment has great potential for ecologically safe and low cost semiconductor processing.

Reactive ion etching lag on high rate oxide etching using high density plasma

In this article, reactive ion etching (RIE) lag effect dependence on total gas flow in contact hole etching is first investigated at a high oxide etch rate using high density plasma. We used surface wave coupled plasma apparatus, which achieves a high density of over 1011 cm−3 and a high oxide etch rate of over 1 μm/min. In the high gas flow etching process, a strong RIE lag is observed. However, the low gas flow etching process suppresses the RIE lag. Total gas flow dominates the RIE‐lag effect, and the oxygen of the etching product plays an important role for reducing the RIE‐lag effect.

0.15 /spl mu/m CMOS with high reliability and performance

0.15 /spl mu/m CMOSFETs with high reliability and performance have been realized. The acceptable power supply voltage V/sub cc/ was estimated to be 1.9 V. A reasonably short ring oscillator delay of 33 ps was obtained for the 1.9 V V/sub cc/, maintaining an 0.4 V threshold voltage. Anomalous surface state generation and V/sub TH/ shift for the pMOS were observed, though the degradation was less severe than the nMOS.<<ETX>>

Si surface study after Ar ion‐assisted Cl2 etching

Silicon surfaces after Ar ion‐assisted etching in Cl2 gas atmosphere were studied for various Ar ion current densities and Cl2 gas pressures. The number of incident Ar ions was varied in 6×1014–3×1016 ions/cm2/s while the number of incident Cl2 molecules was varied in 0–3×1017 molecules/cm2/s. Ar ion acceleration energy was fixed at 1 keV. High etching rate, about 5000 A/min, was observed with a high incident rate of both Ar ions and Cl2 molecules. On the other hand, high etch yield was observed at low incident rate of Ar ions and high incident rate of Cl2 molecules. The amount of surface defects and surface chemical adsorption states, which vary with different etching conditions, were studied by etch pit observation after thermal oxidation followed by Secco‐etching, x‐ray photoelectron spectroscopy (XPS), and reflection high energy electron diffraction (RHEED). Silicon surfaces, etched under high etch yield etching conditions, showed relatively high Si2O3 existence by XPS measurement, and high density et...

Oxide etching using surface wave coupled plasma

Oxide etching was evaluated using a new high-density plasma, which was based on surface wave coupled plasma (SWP). This plasma applicator can uniformly generate microwave plasma over a large area, and it can be formed without quartz tubes or plates. The plasma characteristics of SWP were investigated at the low-pressure region. At the First stage, oxide etching characteristics were evaluated. The SWP oxide etcher had a high etching rate and achieved quarter-micron window etching of vertical profile.

Analysis of Fluorocarbon Film Deposited by Highly Selective Oxide Etching

The influence of fluorocarbon film composition on oxide etching selectivity have been studied in a CHF3/CO mixture-gas plasma, using a magnetron-enhanced reactive ion etching system. The Fluorocarbon-film deposition rate dependence on CO concentration was measured. The Sputtering rate and carbon concentration of fluorocarbon films, which were deposited under various CO concentrations, were investigated. With CO addition, the carbon concentration in the fluorocarbon film increases, and the sputtering rate of the deposited film is reduced. High carbon concentration in a deposited polymer can enhance the selectivity of etching by protecting the Si surface from ion bombardment. In addition, an adequate CO mixing can yield a high selectivity of polymer deposition on a Si surface as compared to an oxide surface, which, in turn, achieves a high selectivity in oxide etching on Si.