Yukinori Kurogi

Ferroelectric field‐effect memory device using Bi4Ti3O12 film

A ferroelectric field‐effect transistor has been investigated using a thin film of bismuth titanate (Bi4Ti3O12) deposited on a Si substrate by rf sputtering. Achievement of the ferroelectric polycrystalline Bi4Ti3O12 films without any cracks necessitates postdeposition heat treatment in air at temperatures ?550 °C for 30 min. The film, heat treated at 650 °C, has a remanent polarization of 4.0 μC/cm2 and a coercive field of about 250 kV/cm at 1 kHz. A FET having a gate structure of Bi4Ti3O12‐SiO2‐Si was fabricated, where the SiO2 served to prevent charge injection from Si into the ferroelectric film. (This process would degrade the retention of memorized states.) The FET can be switched by voltages of as low as 15 V applied to the gate. The on and off states are very stable at room temperature.

Selective Silicon Epitaxy Using Reduced Pressure Technique

Silicon selective epitaxial growth using the SiH2Cl2–HCl–H2 system was successfully accomplished on a window surrounded by fine patterned insulator films as a mask. Surface planarity was obtained at less than 80 Torr reduced pressure. Good selectivity was realized by suitable HCl injection during epitaxial growth. Moreover, it was found that the induced defect density on the epi-layer was less at lower growth temperature.

Low-energy electron energy loss spectroscopy of Cl adsorbed Si(111), Si(100) and Si(110) surfaces

Abstract The chlorine adsorption on Si(111)7×7, Si(100)2×1 and Si(110)16×2 surfaces is studied by low-energy electron energy loss spectroscopy (LEELS), Auger electron spectroscopy (AES) and reflection high energy electron diffraction (RHEED). Different primary electron energies are employed on the EELS measurement to vary the probing depth. The Cl/Si(111) surface shows one conspicuous LEELS peak which is related to the Cl(p z ) state, which forms a σ-like bonding state with the Si(p z ) state. The Cl/Si(100) surface shows two LEELS peaks presenting different depth profiles, which are thought to be related to the Cl(p z ) bonding state and to the Cl(p x , p y ) state, which forms a π-like bonding state. The difference of the LEELS spectra for different substrate orientations is attributable to different adsorption configurations; whereas Cl adatoms sit obliquely on Si atoms on the Si(100) and Si(110) surfaces, Cl adatoms sit on top of Si atoms on the Si(110) surface. The AES and RHEED results to the speculation that Cl adsorption does not function to resolve surface dimers but occurs, at dangling bonds on surface Si atoms and on steps.

Selective silicon epitaxial growth for device-isolation

Abstract Selective silicon epitaxial growth using the SiH 2 Cl 2 / HCl / H 2 system under reduced pressure was accomplished in windows surrounded by a fine patterned insulator film on a silicon substrate. Selectivity, surface planarity, and facet formation were studied as a function of growth pressure, growth temperature, and HCl flow rate during selective epitaxial growth. Defects, which were mostly pairs of stacking faults, were observed along sidewalls. The defect density in the epi-layer decreased with both decreasing growth temperature and increasing HCl flow rate. Electrical properties of p-n junctions fabricated in the epi-layers were investigated. Polysilicon gate MOSFETs were successfully fabricated on the epitaxial silicon layers. It was revealed that the selective epitaxial growth isolation was effective to reduce latch-up susceptibility for CMOS circuits. It has been discovered that the selective epitaxial growth is applicable to fine and deep isolation and can realize submicron geometry isolation for VLSI.

Scaled CMOS technology using SEG isolation and buried well process

An advanced bulk CMOS technology has been developed using the selective epitaxial growth (SEG) isolation technique and buried n-well process. CMOS devices are fabricated on a selective epitaxial layer, isolated by a thick SiO2insulator over the p+substrate. p-channel devices are designed on buried n-wells, formed by introducing a phosphorus ion implantation into the p+substrate before the epitaxial growth. The use of an SiO2sidewall and square side direction is effective for defect-free selective epitaxy. The epitaxial autodoping effect from the p+substrate and the buried layer is estimated to be within less than 1 µm. A 20-nm-thick gate oxide and 500-nm-thick phosphorus-doped polysilicon gate electrode are used for both channel devices. Submicrometer gate CMOS operation is confirmed using the SEG isolation technique. This isolation structure, combined with the buried well, shows large latchup immunity for scaled CMOS circuits.

Molybdenum Etching Using CCl4/O2 Mixture Gas

Molybdenum was etched using CCl4/O2 mixture gas. Typical etch rate is about 80 nm/min, and its relative etch rate ratio to resist AZ1350J was 2: 1. Etch rates of silicon and silicon-dioxide were negligibly small, as compared to molybdenum etch rate. The dissociation process of CCl4/O2 analogous to the dissociation process in CF4/O2 mixture gas plasma was observed. Molybdenum-oxide was detected on the surface of silicon, silicon-dioxide and the resist, which were etched with molybdenum, using Auger electron spectroscopy. The deposited molybdenum-oxide increases the etch selectivity of molybdenum over underlying materials. The lateral etching rate after etching end point was about 13 nm/min, in the typical etching condition. The main reason for the pattern width narrowing in the etching was due to moderate resist slope.

Novel device isolation technology with selective epitaxial growth

A novel device isolation technology for small geometry VLSIs using selective epitaxial growth is described. This isolation structure is composed of an SiO2insulator and an epitaxial silicon selectively grown on a bulk silicon surface surrounded with an SiO2isolation wall using a reduced pressure SiH2Cl2-H2-HCl system. This technology, called SEG (selective epitaxial growth) isolation, offers the potential of both fine and deep isolation with submicrometer size features. Polysilicon gate MOSFETs are successfully fabricated on the epitaxial silicon layer. The subthreshold slopes for p-channel or n-channel devices are confirmed to be consistent with these for conventional devices. Using SEG isolation technology, less channel width variation and small narrow-channel effect are shown by electrical characteristics for MOSFETs. The subthreshold behavior for parasitic field devices with submicrometer geometry gives results applicable to fine isolation.

Si surface study after Ar ion‐assisted Cl2 etching

Silicon surfaces after Ar ion‐assisted etching in Cl2 gas atmosphere were studied for various Ar ion current densities and Cl2 gas pressures. The number of incident Ar ions was varied in 6×1014–3×1016 ions/cm2/s while the number of incident Cl2 molecules was varied in 0–3×1017 molecules/cm2/s. Ar ion acceleration energy was fixed at 1 keV. High etching rate, about 5000 A/min, was observed with a high incident rate of both Ar ions and Cl2 molecules. On the other hand, high etch yield was observed at low incident rate of Ar ions and high incident rate of Cl2 molecules. The amount of surface defects and surface chemical adsorption states, which vary with different etching conditions, were studied by etch pit observation after thermal oxidation followed by Secco‐etching, x‐ray photoelectron spectroscopy (XPS), and reflection high energy electron diffraction (RHEED). Silicon surfaces, etched under high etch yield etching conditions, showed relatively high Si2O3 existence by XPS measurement, and high density et...

CMOS technology using SEG isolation technique

An advanced bulk CMOS process has been developed using SEG (Selective Epitaxial Growth) isolation technique and high impurity concentration substrate, in order to suppress latch-up phenomenon. CMOS devices are fabricated on epitiaxial layer, which is selectively grown over p-type silicon substrate surrounded by a 2 µm thick SiO2insulator, using a reduced pressure SiH2Cl2-H2-HCl system. P-channel devices are formed in an n-well, having 3 µm depth. The gate oxide is 20 nm thick. 400 nm thick phosphorus-doped polysilicon is used as a gate electrode. The transition region for autodoping from p+- substrate to the epitaxial layer is less than 1 µm. This isolation combined with low resistivity substrate is effective to reduce latch-up for CMOS circuits. Submicron gate CMOS operation is confirmed using SEG isolation technique.

Secondary Ion Analysis of Silicon under Ar + Ion Etching in Chlorine and Fluorine Flux

Secondary ion analysis was performed on a silicon surface during Ar+ ion bombardment under simultaneous exposure to chlorine or fluorine flux. The Cl+, Cl2+, F+ and F2+ secondary ion intensities increased with the amount of reactive gas flux. However, other secondary ion intensities, such as SiCl+ and SiF+, decreased at large reactive gas flux. In a large reactive gas flux, the Cl+ and F2+ secondary ion intensities were related to the Si etching yield. The amounts of reactive atoms adsorbed on one silicon atom are the same in the large reactive gas flux region. The etching rate ratios of silicon, silicon dioxide and silicon nitride had almost the same value, no matter how much the Cl2 flux increased. No dependence of the etching rate on the crystalline orientation was observed.