El Mehdi Bazizi

Analysis of USJ Formation with Combined RTA/Laser Annealing Conditions for 28nm High-K/Metal Gate CMOS Technology Using Advanced TCAD for Process and Device Simulation

TCAD process and device simulations are used to gain physical understanding for the integration of laser- annealed junctions into a 28 nm high-k/metal gate first process flow. Spike-RTA (Rapid Thermal Annealing) scaling used for transient enhanced diffusion (TED) suppression and shallow extension formation is investigated. In order to overcome the performance loss due to a reduced RTA, laser anneal (LSA) is introduced after Spike-RTA to form highly activated and ultra shallow junctions (USJ). In this work, the impact of different annealing conditions on the performance of NMOS and PMOS devices is investigated in terms of Vth and Ion/Ioff, considering lateral dopant diffusion and activation.

Advanced TCAD simulation of local mismatch in 14nm CMOS technology FinFETs

Local statistical variability (mismatch) is very important in advanced CMOS technologies critically affecting, among others, SRAM supply and holding voltages, performance and yield. TCAD simulation of statistical variability is essential for identification of variability sources and their control in the technology development and optimization. It also plays an important role in the development of accurate statistical compact models for SRAM design, statistical standard cell characterization and statistical circuit simulation and verification. In this paper we compare the TCAD simulation results of statistical variability in 14nm CMOS FinFET technology with Silicon measurements in order to understand the relative role of key statistical variability sources, to assist the technology optimization and to generate target characteristics for statistical compact model extraction.

RF-pFET in fully depleted SOI demonstrates 420 GHz F T

We report an experimental pFET with 420GHz fT, which to the best of our knowledge is the highest value reported for a silicon pFET. The transconductance is 1800uS/um. The technology is fully depleted silicon on insulator (FDSOI) with the pFET channel formed by SiGe condensation. This outstanding performance is achieved by a combination of layout and process optimization which minimizes capacitance and maximizes compressive strain on the channel. The technology features a high-k metal gate and short gate length (20nm drawn) in addition to the SiGe channel for high mobility.

Optimization of RF-22nm FDSOI figures of merit with 3D TCAD simulation

The aim of this study is to illustrate the efficiency of TCAD for simulating RF devices in advanced technology nodes and identify optimization paths. A strategy involving 3D simulation and a multilayered description of the resistive gate is proposed, followed by a calibration step of the TCAD setup against measurements. Then, various effects impacting the values of the Ft/Fmax RF figures of merit are assessed. At last, thanks to combination of TCAD with Design of Experiments, the sensitivity analysis of the most influent process parameters as well as their interactions is performed.

Versatile technology modeling for 22FDX platform development

The 22FDX platform offered by GLOBALFOUNDRIES consists of a family of differentiated products architected to enable applications across a variety of market segments such as RF & Analog, Ultra-low Power (ULP), and Ultra-low Leakage (ULL). In order to ensure the successful development of these new products, as well as to meet the time-to-market constraints, predictive Technology Computer Aided Design (TCAD) tools have been extensively used to guide development efforts, narrow the experimental conditions and reduce the number of learning cycles. The areas of impact expanded to not only predicting device outcome from process input, but also to topics traditionally not addressed by TCAD. In this paper, we present a comprehensive TCAD that has been deployed to optimize core oxide transistors, define approaches to attain ULL targets, and simultaneously investigate the AC behavior at lower operating voltages while improving RF performance. The all-encompassing co-optimization of process, device and layout has been achieved within the same platform.

Impact of backplane configuration on the statistical variability in 22nm FDSOI CMOS

In this paper, using variation aware device simulation, we study the local device variability and mismatch as affected by statistical variation resulting from differing backplane doping options in fully depleted SOI transistors. It is seen that discrete random doping effects associated with the choice of doping has a direct effect on mismatch, resulting in increased mismatch with larger channel doping. However, it is also seen that increased backplane doping may counter intuitively help to reduce the variability associated with discrete doping due modification of the electrostatic screening of the source/drain extensions.

USJ engineering impacts on FinFETs and RDF investigation using full 3D process/device simulation

The impacts of FinFET channel and extension S/D region implantations on relevant device parameters such as electrostatic control and Vth mismatch (MM) are investigated. We used 3D TCAD process and device simulations to gain physical understanding and to optimize the performance/variability of bulk-FinFETs. For the first time, the full FinFET process flow simulation was performed using diffusion, activation and segregation models identical to those used in planar nodes. In this work a wide range of implantation and anneal splits is used to demonstrate the 3D simulation accuracy. After achieving good agreement with experiments in terms of Vth and Ion/Ioff, considering lateral dopant diffusion and activation, the simulation was used to investigate SRAM random doping fluctuation RDF.

Advanced TCAD for Predictive FinFETs Vth Mismatch Using Full 3D Process/Device Simulation

Predictive TCAD tool is crucial for several reasons such as to provide pre-silicon data, shorten the technology development cycle and reduce the fabrication cost. In this paper, advanced 3D TCAD process and device simulations is used to gain physical understanding and to optimize the performance/variability of bulk-FinFETs. For the first time, the full FinFET process flow simulation was performed using diffusion, activation and segregation models identical to those used in planar nodes. In this work a wide range of implantation and anneal splits is used to demonstrate the 3D simulation accuracy. After achieving good agreement with experiments in terms of Vth and Ion/Ioff, considering lateral dopant diffusion and activation, the simulation was used to investigate SRAM random doping fluctuation RDF.

TCAD Modeling for next generation CMOS devices

The complexity of the physics involved in the fabrication of 3D advanced nano-devices, promotes the daily use of advanced simulation tools. TCAD will be needed not only to optimize the transistors and support the device and process integration teams, but also to understand the new materials impact on the transistor performance. To achieve such goal, new simulation paradigms are required, affecting the way TCAD is used. Actually, the 3D TCAD, already used for silicon nodes, faces a limitation of present continuum tools for process and device simulations. The constant reduction of the transistor dimensions and the point defects-dopants interaction with multiple interfaces make Kinetic Monte Carlo a suitable tool for predictive 3D process modeling. On the device side, the 3D confinement of the device and the discrete doping profiles require accurate modeling of the scattering mechanisms in the silicon channel which makes 3D Monte Carlo simulation attractive However, for the simulation of new materials in the channel and source/drain of the Finfet, 3D Monte Carlo simulation becomes mandatory for the transport modeling. In this paper, we will review these different aspects of the TCAD needed for the 3D Tri-gate devices.